cpu/simple/timing.cc

135         if (threadInfo[tid]->thread->status() == ThreadContext::Active) {
177     M5_VAR_USED SimpleThread* thread = t_info.thread;
184     assert(thread->microPC() == 0);
262     SimpleThread* thread = t_info.thread;
269         TheISA::handleLockedRead(thread, pkt->req);
272         Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt);
292     SimpleThread* thread = t_info.thread;
307             do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask);
424     SimpleThread* thread = t_info.thread;
428     const Addr pc = thread->instAddr();
437         thread->contextId());
461         thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode);
462         thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode);
468         thread->dtb->translateTiming(req, thread->getTC(), translation, mode);
478     SimpleThread* thread = t_info.thread;
482         Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
502     SimpleThread* thread = t_info.thread;
506     const Addr pc = thread->instAddr();
523         thread->contextId());
550         thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode);
551         thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode);
557         thread->dtb->translateTiming(req, thread->getTC(), translation, mode);
570     SimpleThread* thread = t_info.thread;
574     const Addr pc = thread->instAddr();
582                             dataMasterId(), pc, thread->contextId(),
608     thread->dtb->translateTiming(req, thread->getTC(), translation, mode);
621             TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt,
656     // Change thread if multi-threaded
660     SimpleThread* thread = t_info.thread;
673     TheISA::PCState pcState = thread->pcState();
681         ifetch_req->setContext(thread->contextId());
684         thread->itb->translateTiming(ifetch_req, thread->getTC(),
961             TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);