cpu/simple/timing.cc

81       dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0),
275         dcache_pkt = NULL;
278         dcache_pkt = pkt;
282         dcache_pkt = NULL;
284     return dcache_pkt == NULL;
298         assert(!dcache_pkt);
314             dcache_pkt = pkt;
331         assert(!dcache_pkt);
346         dcache_pkt = pkt1;
351             dcache_pkt = pkt2;
480     const RequestPtr &req = dcache_pkt->req;
482         Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
483         new IprEvent(dcache_pkt, this, clockEdge(delay));
485         dcache_pkt = NULL;
486     } else if (!dcachePort.sendTimingReq(dcache_pkt)) {
491         dcache_pkt = NULL;
493     return dcache_pkt == NULL;
1008     assert(cpu->dcache_pkt != NULL);
1010     PacketPtr tmp = cpu->dcache_pkt;
1029                 cpu->dcache_pkt = tmp;
1037                 cpu->dcache_pkt = NULL;
1043         cpu->dcache_pkt = NULL;