Lines Matching refs:val
188 setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
193 thread->setIntReg(reg.index(), val);
210 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
215 thread->setFloatReg(reg.index(), val);
241 const VecRegContainer& val) override
246 thread->setVecReg(reg, val);
289 const LD& val)
294 return thread->setVecLane(reg, val);
299 const LaneData<LaneSize::Byte>& val) override
300 { return setVecLaneOperandT(si, idx, val); }
304 const LaneData<LaneSize::TwoByte>& val) override
305 { return setVecLaneOperandT(si, idx, val); }
309 const LaneData<LaneSize::FourByte>& val) override
310 { return setVecLaneOperandT(si, idx, val); }
314 const LaneData<LaneSize::EightByte>& val) override
315 { return setVecLaneOperandT(si, idx, val); }
331 const VecElem val) override
336 thread->setVecElem(reg, val);
359 const VecPredRegContainer& val) override
364 thread->setVecPredReg(reg, val);
377 setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
382 thread->setCCReg(reg.index(), val);
395 setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
400 thread->setMiscReg(reg.index(), val);
419 setMiscReg(int misc_reg, RegVal val) override
422 thread->setMiscReg(misc_reg, val);
432 pcState(const PCState &val) override
434 thread->pcState(val);
518 setPredicate(bool val) override
520 thread->setPredicate(val);
523 cpu->traceData->setPredicate(val);
534 setMemAccPredicate(bool val) override
536 thread->setMemAccPredicate(val);