cpu/simple/exec_context.hh

181         const RegId& reg = si->srcRegIdx(idx);
182         assert(reg.isIntReg());
183         return thread->readIntReg(reg.index());
191         const RegId& reg = si->destRegIdx(idx);
192         assert(reg.isIntReg());
193         thread->setIntReg(reg.index(), val);
202         const RegId& reg = si->srcRegIdx(idx);
203         assert(reg.isFloatReg());
204         return thread->readFloatReg(reg.index());
213         const RegId& reg = si->destRegIdx(idx);
214         assert(reg.isFloatReg());
215         thread->setFloatReg(reg.index(), val);
223         const RegId& reg = si->srcRegIdx(idx);
224         assert(reg.isVecReg());
225         return thread->readVecReg(reg);
233         const RegId& reg = si->destRegIdx(idx);
234         assert(reg.isVecReg());
235         return thread->getWritableVecReg(reg);
244         const RegId& reg = si->destRegIdx(idx);
245         assert(reg.isVecReg());
246         thread->setVecReg(reg, val);
257         const RegId& reg = si->srcRegIdx(idx);
258         assert(reg.isVecReg());
259         return thread->readVecLane<VecElem>(reg);
292         const RegId& reg = si->destRegIdx(idx);
293         assert(reg.isVecReg());
294         return thread->setVecLane(reg, val);
323         const RegId& reg = si->srcRegIdx(idx);
324         assert(reg.isVecElem());
325         return thread->readVecElem(reg);
334         const RegId& reg = si->destRegIdx(idx);
335         assert(reg.isVecElem());
336         thread->setVecElem(reg, val);
343         const RegId& reg = si->srcRegIdx(idx);
344         assert(reg.isVecPredReg());
345         return thread->readVecPredReg(reg);
352         const RegId& reg = si->destRegIdx(idx);
353         assert(reg.isVecPredReg());
354         return thread->getWritableVecPredReg(reg);
362         const RegId& reg = si->destRegIdx(idx);
363         assert(reg.isVecPredReg());
364         thread->setVecPredReg(reg, val);
371         const RegId& reg = si->srcRegIdx(idx);
372         assert(reg.isCCReg());
373         return thread->readCCReg(reg.index());
380         const RegId& reg = si->destRegIdx(idx);
381         assert(reg.isCCReg());
382         thread->setCCReg(reg.index(), val);
389         const RegId& reg = si->srcRegIdx(idx);
390         assert(reg.isMiscReg());
391         return thread->readMiscReg(reg.index());
398         const RegId& reg = si->destRegIdx(idx);
399         assert(reg.isMiscReg());
400         thread->setMiscReg(reg.index(), val);