Lines Matching defs:val
265 O3ThreadContext<Impl>::setIntRegFlat(RegIndex reg_idx, RegVal val)
267 cpu->setArchIntReg(reg_idx, val, thread->threadId());
274 O3ThreadContext<Impl>::setFloatRegFlat(RegIndex reg_idx, RegVal val)
276 cpu->setArchFloatReg(reg_idx, val, thread->threadId());
284 RegIndex reg_idx, const VecRegContainer& val)
286 cpu->setArchVecReg(reg_idx, val, thread->threadId());
294 const ElemIndex& elemIndex, const VecElem& val)
296 cpu->setArchVecElem(idx, elemIndex, val, thread->threadId());
303 const VecPredRegContainer& val)
305 cpu->setArchVecPredReg(reg_idx, val, thread->threadId());
312 O3ThreadContext<Impl>::setCCRegFlat(RegIndex reg_idx, RegVal val)
314 cpu->setArchCCReg(reg_idx, val, thread->threadId());
321 O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
323 cpu->pcState(val, thread->threadId());
330 O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
332 cpu->pcState(val, thread->threadId());
346 O3ThreadContext<Impl>::setMiscRegNoEffect(RegIndex misc_reg, RegVal val)
348 cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
355 O3ThreadContext<Impl>::setMiscReg(RegIndex misc_reg, RegVal val)
357 cpu->setMiscReg(misc_reg, val, thread->threadId());