cpu/o3/lsq_unit.hh

101         LSQRequest* req;
109             : inst(nullptr), req(nullptr), _size(0), _valid(false)
116             if (req != nullptr) {
117                 req->freeLSQEntry();
118                 req = nullptr;
126             if (req != nullptr) {
127                 req->freeLSQEntry();
129             req = nullptr;
142         LSQRequest* request() { return req; }
143         void setRequest(LSQRequest* r) { req = r; }
144         bool hasRequest() { return req != nullptr; }
574     Fault read(LSQRequest *req, int load_idx);
577     Fault write(LSQRequest *req, uint8_t *data, int store_idx);
613 LSQUnit<Impl>::read(LSQRequest *req, int load_idx)
618     load_req.setRequest(req);
628     if (req->mainRequest()->isStrictlyOrdered() &&
643         req->discard();
652             req->mainRequest()->getPaddr(), req->isSplit() ? " split" : "");
654     if (req->mainRequest()->isLLSC()) {
659         TheISA::handleLockedRead(load_inst.get(), req->mainRequest());
663     if (req->mainRequest()->isMmappedIpr()) {
668         PacketPtr main_pkt = new Packet(req->mainRequest(), MemCmd::ReadReq);
672         Cycles delay = req->handleIprRead(thread, main_pkt);
700             auto req_s = req->mainRequest()->getVaddr();
701             auto req_e = req_s + req->mainRequest()->getSize();
716                 !req->mainRequest()->isLLSC()) {
719                 int shift_amt = req->mainRequest()->getVaddr() -
725                         new uint8_t[req->mainRequest()->getSize()];
729                             req->mainRequest()->getSize());
733                         req->mainRequest()->getSize());
737                         req->mainRequest()->getVaddr());
739                 PacketPtr data_pkt = new Packet(req->mainRequest(),
743                 if (req->isAnyOutstandingRequest()) {
744                     assert(req->_numOutstandingPackets > 0);
749                     req->discardSenderState();
767                 (!req->mainRequest()->isLLSC() &&
773                 (req->mainRequest()->isLLSC() &&
811                         store_it._idx, req->mainRequest()->getVaddr());
814                 req->discard();
827         load_inst->memData = new uint8_t[req->mainRequest()->getSize()];
837     if (req->senderState() == nullptr) {
842         state->isSplit = req->isSplit();
843         req->senderState(state);
845     req->buildPackets();
846     req->sendPacketToCache();
847     if (!req->isSent())
855 LSQUnit<Impl>::write(LSQRequest *req, uint8_t *data, int store_idx)
861             store_idx - 1, req->request()->getPaddr(), storeQueue.head() - 1,
864     storeQueue[store_idx].setRequest(req);
865     unsigned size = req->_size;
868         req->mainRequest()->getFlags() & Request::STORE_NO_DATA;
873     if (!(req->request()->getFlags() & Request::CACHE_BLOCK_ZERO) &&
874         !req->request()->isCacheMaintenance() &&
875         !req->request()->isAtomic())