Lines Matching refs:val

149     setMiscReg(int misc_reg, RegVal val) override
159 _destMiscRegVal[idx] = val;
166 _destMiscRegVal[_numDestMiscRegs] = val;
185 setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
189 setMiscReg(reg.index(), val);
330 setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
332 return cpu->template setVecLane(_destRegIdx[idx], val);
336 const LaneData<LaneSize::Byte>& val) override
338 return setVecLaneOperandT(si, idx, val);
342 const LaneData<LaneSize::TwoByte>& val) override
344 return setVecLaneOperandT(si, idx, val);
348 const LaneData<LaneSize::FourByte>& val) override
350 return setVecLaneOperandT(si, idx, val);
354 const LaneData<LaneSize::EightByte>& val) override
356 return setVecLaneOperandT(si, idx, val);
387 setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
389 this->cpu->setIntReg(this->_destRegIdx[idx], val);
390 BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
394 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
396 this->cpu->setFloatReg(this->_destRegIdx[idx], val);
397 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
402 const VecRegContainer& val) override
404 this->cpu->setVecReg(this->_destRegIdx[idx], val);
405 BaseDynInst<Impl>::setVecRegOperand(si, idx, val);
409 const VecElem val) override
412 this->cpu->setVecElem(this->_destRegIdx[reg_idx], val);
413 BaseDynInst<Impl>::setVecElemOperand(si, idx, val);
418 const VecPredRegContainer& val) override
420 this->cpu->setVecPredReg(this->_destRegIdx[idx], val);
421 BaseDynInst<Impl>::setVecPredRegOperand(si, idx, val);
424 void setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
426 this->cpu->setCCReg(this->_destRegIdx[idx], val);
427 BaseDynInst<Impl>::setCCRegOperand(si, idx, val);