Lines Matching defs:params

82 BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
83 : BaseCPU(params)
94 FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
95 : BaseO3CPU(params),
96 itb(params->itb),
97 dtb(params->dtb),
106 fetch(this, params),
107 decode(this, params),
108 rename(this, params),
109 iew(this, params),
110 commit(this, params),
114 vecMode(RenameMode<TheISA::ISA>::init(params->isa[0])),
115 regFile(params->numPhysIntRegs,
116 params->numPhysFloatRegs,
117 params->numPhysVecRegs,
118 params->numPhysVecPredRegs,
119 params->numPhysCCRegs,
124 rob(this, params),
131 timeBuffer(params->backComSize, params->forwardComSize),
132 fetchQueue(params->backComSize, params->forwardComSize),
133 decodeQueue(params->backComSize, params->forwardComSize),
134 renameQueue(params->backComSize, params->forwardComSize),
135 iewQueue(params->backComSize, params->forwardComSize),
137 params->backComSize + params->forwardComSize,
138 params->activity),
141 system(params->system),
144 if (!params->switched_out) {
150 if (params->checker) {
151 BaseCPU *temp_checker = params->checker;
154 checker->setSystem(params->system);
202 active_threads = params->workload.size();
212 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
213 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
214 assert(params->numPhysVecRegs >= numThreads * TheISA::NumVecRegs);
215 assert(params->numPhysVecPredRegs >= numThreads * TheISA::NumVecPredRegs);
216 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
223 isa[tid] = params->isa[tid];
317 if (tid < params->workload.size()) {
322 tid, params->workload[tid]);
347 if (params->checker) {
367 if (!params->switched_out && interrupts.empty()) {
602 if (FullSystem && !params()->switched_out) {