cpu/minor/lsq.hh

169             RequestIssuing, /* Load/store issued to memory in the requests
180                 completed loads, TLB faults and skipped requests whose
252         /** This request, once processed by the requests/transfers
277     /** Special request types that don't actually issue memory requests */
300         /** Never sends any requests */
314     /** FailedDataRequest represents requests from instructions that
315      *  failed their predicates but need to ride the requests/transfers
338     /** SingleDataRequest is used for requests that don't fragment */
428          *  requests can be sent for address translation */
431         /** Make the packets to go with the requests so they can be sent to
437          *  numFragments) to complete all this requests' fragments' address
478         /** Queue of store requests on their way to memory */
517          *  numUnissuedAccesses.  Does not count barrier requests as they
548     /** The LSQ consists of three queues: requests, transfers and the
556     /** requests contains LSQRequests which have been issued to the TLB by
559      *  have a physical address, requests at the head of requests can be
565      *  'transfers' in order) and all other transfers are stalled in requests
568     LSQQueue requests;
581      * Before trying to issue a cacheable read from 'requests' to memory,
592      *  requests queue and are in the 'wild' in the memory system and who
594      *  accesses.  This is a count of the number of in-flight requests
599     /** Number of requests in the DTLB in the requests queue */
611     /** The request (from either requests or the store buffer) which is
620      *  head of the requests queue.  Also tries to move the request
663     bool canRequest() { return requests.unreservedRemainingSpace() != 0; }
707     /** Single interface for readMem/writeMem/amoMem to issue requests into