Lines Matching refs:request
67 request(),
74 request = std::make_shared<Request>();
125 /* 'end' here means the address of the byte just past the request
145 return containsAddrRangeOf(request->getPaddr(), request->getSize(),
146 other_request->request->getPaddr(), other_request->request->getSize());
164 DPRINTFS(MinorMem, (&port), "Setting state from %d to %d for request:"
269 " request: %s delayed:%d %s\n", *inst, isTranslationDelayed,
298 const auto &byteEnable = request->getByteEnable();
305 DPRINTFS(MinorMem, (&port), "Submitting DTLB request\n");
306 /* Submit the translation request. The response will come through
310 request, thread, this, (isLoad ? BaseTLB::Read : BaseTLB::Write));
339 " %d of request: %s delayed:%d %s\n", expected_fragment_index,
354 " %d of request: %s\n",
398 /* Don't know how many elements are needed until the request is
414 Addr base_addr = request->getVaddr();
415 unsigned int whole_size = request->getSize();
464 /* Just past the last address in the request */
467 auto& byte_enable = request->getByteEnable();
492 fragment->setContext(request->contextId());
495 fragment_addr, fragment_size, request->getFlags(),
496 request->masterId(),
497 request->getPC());
506 fragment_addr, fragment_size, request->getFlags(),
507 request->masterId(),
508 request->getPC());
517 " size: %d (whole request addr: 0x%x size: %d) %s\n",
536 Addr base_addr = request->getVaddr();
538 DPRINTFS(MinorMem, (&port), "Making packets for request: %s\n", *inst);
546 DPRINTFS(MinorMem, (&port), "Making packet %d for request: %s"
571 /* Accumulate flags in parent request */
572 request->setFlags(fragment->getFlags());
576 /* Get the physical address for the whole request/packet from the first
578 request->setPaddr(fragmentRequests[0]->getPaddr());
632 request->getVaddr() - response->req->getVaddr(),
638 /* Skip because we already knew the request had faulted or been
652 data = new uint8_t[request->getSize()];
658 data + (response->req->getVaddr() - request->getVaddr()),
681 packet->needsResponse(), packet->getSize(), request->getSize(),
684 /* A request can become complete by several paths, this is a sanity
687 data = new uint8_t[request->getSize()];
692 std::memcpy(packet->getPtr<uint8_t>(), data, request->getSize());
708 DPRINTFS(MinorMem, (&port), "Submitting DTLB request for fragment: %d\n",
727 LSQ::StoreBuffer::deleteRequest(LSQRequestPtr request)
729 auto found = std::find(slots.begin(), slots.end(), request);
732 DPRINTF(MinorMem, "Deleting request: %s %s %s from StoreBuffer\n",
733 request, *found, *(request->inst));
736 delete request;
741 LSQ::StoreBuffer::insert(LSQRequestPtr request)
745 " inst: %s\n", name(), *(request->inst));
748 DPRINTF(MinorMem, "Pushing store: %s into store buffer\n", request);
752 if (request->state != LSQRequest::Complete)
753 request->setState(LSQRequest::StoreInStoreBuffer);
755 slots.push_back(request);
763 LSQ::StoreBuffer::canForwardDataToLoad(LSQRequestPtr request,
771 * and try to find a slot whose address range overlaps this request */
779 slot->inst->id.threadId == request->inst->id.threadId &&
781 AddrRangeCoverage coverage = slot->containsAddrRangeOf(request);
787 request->request->getPaddr(), request->request->getSize(),
788 slot->request->getPaddr(), slot->request->getSize());
816 Addr load_addr = load->request->getPaddr();
817 Addr store_addr = store->request->getPaddr();
820 unsigned int load_size = load->request->getSize();
834 LSQ::StoreBuffer::countIssuedStore(LSQRequestPtr request)
838 if (!request->isBarrier())
881 LSQRequestPtr request = *i;
883 DPRINTF(MinorMem, "Considering request: %s, sentAllPackets: %d"
885 *(request->inst), request->sentAllPackets(),
886 request->state);
888 if (request->isBarrier() && request->isComplete()) {
891 } else if (!(request->state == LSQRequest::StoreBufferIssuing &&
892 request->sentAllPackets()))
894 DPRINTF(MinorMem, "Trying to send request: %s to memory"
895 " system\n", *(request->inst));
897 if (lsq.tryToSend(request)) {
898 countIssuedStore(request);
917 /* Not already sent to the store buffer as a store request? */
937 LSQRequestPtr request = slots[i];
939 request->reportData(os);
959 LSQ::tryToSendToTransfers(LSQRequestPtr request)
967 if (request->state == LSQRequest::InTranslation) {
973 assert(request->state == LSQRequest::Translated ||
974 request->state == LSQRequest::RequestIssuing ||
975 request->state == LSQRequest::Failed ||
976 request->state == LSQRequest::Complete);
978 if (requests.empty() || requests.front() != request) {
985 DPRINTF(MinorMem, "No space to insert request into transfers"
990 if (request->isComplete() || request->state == LSQRequest::Failed) {
992 " queue\n", (request->isComplete() ? "completed" : "failed"));
993 request->setState(LSQRequest::Complete);
994 request->setSkipped();
995 moveFromRequestsToTransfers(request);
999 if (!execute.instIsRightStream(request->inst)) {
1002 if (request->hasPacketsInMemSystem()) {
1004 " waiting for responses before aborting request\n");
1007 " aborting request\n");
1008 request->setState(LSQRequest::Complete);
1009 request->setSkipped();
1010 moveFromRequestsToTransfers(request);
1015 if (request->inst->translationFault != NoFault) {
1016 if (request->inst->staticInst->isPrefetch()) {
1019 DPRINTF(MinorMem, "Moving faulting request into the transfers"
1021 request->setState(LSQRequest::Complete);
1022 request->setSkipped();
1023 moveFromRequestsToTransfers(request);
1027 bool is_load = request->isLoad;
1028 bool is_llsc = request->request->isLLSC();
1029 bool is_swap = request->request->isSwap();
1030 bool is_atomic = request->request->isAtomic();
1031 bool bufferable = !(request->request->isStrictlyOrdered() ||
1036 DPRINTF(MinorMem, "Load request with stores still in transfers"
1042 if (bufferable && !request->request->isMmappedIpr()) {
1043 request->setState(LSQRequest::StoreToStoreBuffer);
1044 moveFromRequestsToTransfers(request);
1054 if (!execute.instIsHeadInst(request->inst)) {
1062 if (storeBuffer.canForwardDataToLoad(request, forwarding_slot) !=
1065 // There's at least another request that targets the same
1067 // request is non-bufferable (e.g., strictly ordered or atomic),
1068 // we must wait for the other request in the storeBuffer to
1069 // complete before we can issue this non-bufferable request.
1081 * False: skip the memory and push a packet for this request onto
1090 storeBuffer.canForwardDataToLoad(request,
1095 /* Forward data from the store buffer into this request and
1096 * repurpose this request's packet into a response packet */
1097 storeBuffer.forwardStoreData(request, forwarding_slot);
1098 request->packet->makeResponse();
1116 DPRINTF(MinorMem, "Can't send request to memory system yet\n");
1120 SimpleThread &thread = *cpu.threads[request->inst->id.threadId];
1123 ExecContext context(cpu, thread, execute, request->inst);
1127 TheISA::handleLockedRead(&context, request->request);
1130 request->request, cacheBlockMask);
1143 DPRINTF(MinorMem, "Can't send request to memory system yet\n");
1149 if (!bufferable && !request->issuedToMemory) {
1151 request->issuedToMemory = true;
1154 if (tryToSend(request)) {
1155 moveFromRequestsToTransfers(request);
1158 request->setState(LSQRequest::Complete);
1159 moveFromRequestsToTransfers(request);
1164 LSQ::tryToSend(LSQRequestPtr request)
1169 DPRINTF(MinorMem, "Can't send request: %s yet, no space in memory\n",
1170 *(request->inst));
1172 PacketPtr packet = request->getHeadPacket();
1174 DPRINTF(MinorMem, "Trying to send request: %s addr: 0x%x\n",
1175 *(request->inst), packet->req->getVaddr());
1181 if (request->request->isMmappedIpr()) {
1184 request->request->contextId()));
1186 if (request->isLoad) {
1187 DPRINTF(MinorMem, "IPR read inst: %s\n", *(request->inst));
1190 DPRINTF(MinorMem, "IPR write inst: %s\n", *(request->inst));
1194 request->stepToNextPacket();
1195 ret = request->sentAllPackets();
1199 *(request->inst));
1203 request->setState(LSQRequest::Complete);
1205 request->setState(LSQRequest::RequestIssuing);
1207 DPRINTF(MinorMem, "Sent data memory request\n");
1211 request->stepToNextPacket();
1213 ret = request->sentAllPackets();
1215 switch (request->state) {
1218 /* Fully or partially issued a request in the transfers
1220 request->setState(LSQRequest::RequestIssuing);
1224 /* Fully or partially issued a request in the store
1226 request->setState(LSQRequest::StoreBufferIssuing);
1229 panic("Unrecognized LSQ request state %d.", request->state);
1235 "Sending data memory request - needs retry\n");
1239 retryRequest = request;
1241 switch (request->state) {
1244 request->setState(LSQRequest::RequestNeedsRetry);
1248 request->setState(LSQRequest::StoreBufferNeedsRetry);
1251 panic("Unrecognized LSQ request state %d.", request->state);
1257 threadSnoop(request);
1263 LSQ::moveFromRequestsToTransfers(LSQRequestPtr request)
1265 assert(!requests.empty() && requests.front() == request);
1272 if (!request->isLoad)
1276 transfers.push(request);
1289 LSQRequestPtr request =
1294 *(request->inst), response->getAddr(),
1301 *request->inst);
1304 switch (request->state) {
1307 /* Response to a request from the transfers queue */
1308 request->retireResponse(response);
1311 request->hasPacketsInMemSystem(), request->isComplete());
1316 /* Response to a request from the store buffer */
1317 request->retireResponse(response);
1321 if (request->isComplete()) {
1322 if (!request->isBarrier()) {
1323 storeBuffer.deleteRequest(request);
1326 " leaving the request as it is also a barrier\n",
1327 *(request->inst));
1349 DPRINTF(MinorMem, "Received retry request\n");
1363 panic("Unrecognized retry request state %d.", retryRequest->state);
1369 * issue a memory request and either succeed for this
1370 * request or return the LSQ back to MemoryNeedsRetry */
1373 /* Try to resend the request */
1375 /* Successfully sent, need to move the request */
1386 panic("Unrecognized retry request state %d.", retryRequest->state);
1482 LSQRequestPtr request = transfers.front();
1486 if (request->inst->id == inst->id) {
1487 bool complete = request->isComplete();
1489 bool to_store_buffer = request->state ==
1492 if ((complete && !(request->isBarrier() && !can_store)) ||
1495 ret = request;
1525 DPRINTF(MinorMem, "Deleting %s request: %s\n",
1534 LSQ::sendStoreToStoreBuffer(LSQRequestPtr request)
1536 assert(request->state == LSQRequest::StoreToStoreBuffer);
1539 *(request->inst));
1541 request->inst->inStoreBuffer = true;
1543 storeBuffer.insert(request);
1595 panic("Do not expect cross-cache-line atomic memory request\n");
1598 LSQRequestPtr request;
1600 /* Copy given data into the request. The request will pass this to the
1604 DPRINTF(MinorMem, "Pushing request (%s) addr: 0x%x size: %d flags:"
1623 request = new SplitDataRequest(
1626 request = new SingleDataRequest(
1634 request->request->setContext(cid);
1635 request->request->setVirt(0 /* asid */,
1639 request->request->setByteEnable(byteEnable);
1641 requests.push(request);
1643 request->startAddrTranslation();
1651 LSQRequestPtr request = new FailedDataRequest(*this, inst);
1652 requests.push(request);
1679 makePacketForRequest(const RequestPtr &request, bool isLoad,
1682 PacketPtr ret = isLoad ? Packet::createRead(request)
1683 : Packet::createWrite(request);
1690 } else if (!request->isCacheMaintenance()) {
1720 packet = makePacketForRequest(request, isLoad, this, data);
1765 LSQ::threadSnoop(LSQRequestPtr request)
1770 ThreadID req_tid = request->inst->id.threadId;
1771 PacketPtr pkt = request->packet;