cpu/minor/fetch1.hh

43  *  Fetch1 is responsible for fetching "lines" from memory and passing
61 class Fetch1 : public Named
69         Fetch1 &fetch;
72         IcachePort(std::string name, Fetch1 &fetch_, MinorCPU &cpu) :
107         Fetch1 &fetch;
170         FetchRequest(Fetch1 &fetch_, InstId id_, TheISA::PCState pc_) :
204     /** IcachePort to pass to the CPU.  Fetch1 is the only module that uses
298     /** Queue of address translated requests from Fetch1 */
322         Fetch1::FetchState state);
385     Fetch1(const std::string &name_,
394     /** Returns the IcachePort owned by this Fetch1 */
405     /** Is this stage drained?  For Fetch1, draining is initiated by