cpu/minor/fetch1.cc

153     /* If line_offset != 0, a request is pushed for the remainder of the
165     FetchRequestPtr request = new FetchRequest(*this, request_id, thread.pc);
171     request->request->setContext(cpu.threads[tid]->getTC()->contextId());
172     request->request->setVirt(0 /* asid */,
177     DPRINTF(Fetch, "Submitting ITLB request\n");
180     request->state = FetchRequest::InTranslation;
184     requests.push(request);
186     /* Submit the translation request.  The response will come
187      *  through finish/markDelayed on this request as it bears
189     cpu.threads[request->id.threadId]->itb->translateTiming(
190         request->request,
191         cpu.getContext(request->id.threadId),
192         request, BaseTLB::Execute);
231     packet = new Packet(request, MemCmd::ReadReq);
261             (response->request->hasPaddr() ?
262                 response->request->getPaddr() : 0),
263             response->request->getVaddr());
283 Fetch1::tryToSendToTransfers(FetchRequestPtr request)
285     if (!requests.empty() && requests.front() != request) {
291     if (request->state == FetchRequest::InTranslation) {
297     if (request->isDiscardable() || request->fault != NoFault) {
301         request->state = FetchRequest::Complete;
302         moveFromRequestsToTransfers(request);
307     } else if (request->state == FetchRequest::Translated) {
308         if (!request->packet)
309             request->makePacket();
311         /* Ensure that the packet won't delete the request */
312         assert(request->packet->needsResponse());
314         if (tryToSend(request))
315             moveFromRequestsToTransfers(request);
322 Fetch1::moveFromRequestsToTransfers(FetchRequestPtr request)
324     assert(!requests.empty() && requests.front() == request);
327     transfers.push(request);
331 Fetch1::tryToSend(FetchRequestPtr request)
335     if (icachePort.sendTimingReq(request->packet)) {
339         request->packet = NULL;
340         request->state = FetchRequest::RequestIssuing;
345         DPRINTF(Fetch, "Issued fetch request to memory: %s\n",
346             request->id);
352             request->id);
401     const RequestPtr &request M5_VAR_USED = response->request;
405             response->id, request->getVaddr());
408             response->id, request->getVaddr(), response->fault->name());
411             response->id, request->getSize(),
412             request->getVaddr(), request->getPaddr());
554     line.lineBaseAddr = response->request->getVaddr();
604             /* The streamSeqNum tagging in request/response ->req should handle