Lines Matching defs:val
200 setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
204 thread.setIntReg(reg.index(), val);
208 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
212 thread.setFloatReg(reg.index(), val);
217 const TheISA::VecRegContainer& val) override
221 thread.setVecReg(reg, val);
226 const TheISA::VecPredRegContainer& val) override
230 thread.setVecPredReg(reg, val);
278 setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
282 return thread.setVecLane(reg, val);
286 const LaneData<LaneSize::Byte>& val) override
288 setVecLaneOperandT(si, idx, val);
292 const LaneData<LaneSize::TwoByte>& val) override
294 setVecLaneOperandT(si, idx, val);
298 const LaneData<LaneSize::FourByte>& val) override
300 setVecLaneOperandT(si, idx, val);
304 const LaneData<LaneSize::EightByte>& val) override
306 setVecLaneOperandT(si, idx, val);
312 const TheISA::VecElem val) override
316 thread.setVecElem(reg, val);
326 setPredicate(bool val) override
328 thread.setPredicate(val);
338 setMemAccPredicate(bool val) override
340 thread.setMemAccPredicate(val);
350 pcState(const TheISA::PCState &val) override
352 thread.pcState(val);
368 setMiscReg(int misc_reg, RegVal val) override
370 thread.setMiscReg(misc_reg, val);
382 setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
386 return thread.setMiscReg(reg.index(), val);
424 setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
428 thread.setCCReg(reg.index(), val);