cpu/kvm/x86_cpu.cc

692 #define APPLY_IREG(kreg, mreg) regs.kreg = tc->readIntReg(mreg)
696     regs.rip = tc->instAddr() - tc->readMiscReg(MISCREG_CS_BASE);
704     regs.rflags = X86ISA::getRFlags(tc);
710 setKvmSegmentReg(ThreadContext *tc, struct kvm_segment &kvm_seg,
713     SegAttr attr(tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(index)));
715     kvm_seg.base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(index));
716     kvm_seg.limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(index));
717     kvm_seg.selector = tc->readMiscRegNoEffect(MISCREG_SEG_SEL(index));
735 setKvmDTableReg(ThreadContext *tc, struct kvm_dtable &kvm_dtable,
738     kvm_dtable.base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(index));
739     kvm_dtable.limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(index));
759 #define APPLY_SREG(kreg, mreg) sregs.kreg = tc->readMiscRegNoEffect(mreg)
760 #define APPLY_SEGMENT(kreg, idx) setKvmSegmentReg(tc, sregs.kreg, idx)
761 #define APPLY_DTABLE(kreg, idx) setKvmDTableReg(tc, sregs.kreg, idx)
806     RFLAGS rflags_nocc(tc->readMiscReg(MISCREG_RFLAGS));
824 updateKvmStateFPUCommon(ThreadContext *tc, T &fpu)
826     fpu.mxcsr = tc->readMiscRegNoEffect(MISCREG_MXCSR);
827     fpu.fcw = tc->readMiscRegNoEffect(MISCREG_FCW);
830     fpu.fsw = tc->readMiscReg(MISCREG_FSW);
832     uint64_t ftw(tc->readMiscRegNoEffect(MISCREG_FTW));
835     fpu.last_opcode = tc->readMiscRegNoEffect(MISCREG_FOP);
841                     tc->readFloatReg(FLOATREG_FPR(reg_idx))));
851             tc->readFloatReg(FLOATREG_XMM_LOW(i));
853             tc->readFloatReg(FLOATREG_XMM_HIGH(i));
866     updateKvmStateFPUCommon(tc, fpu);
868     if (tc->readMiscRegNoEffect(MISCREG_FISEG))
871     fpu.last_ip = tc->readMiscRegNoEffect(MISCREG_FIOFF);
873     if (tc->readMiscRegNoEffect(MISCREG_FOSEG))
876     fpu.last_dp = tc->readMiscRegNoEffect(MISCREG_FOOFF);
891     updateKvmStateFPUCommon(tc, xsave);
893     if (tc->readMiscRegNoEffect(MISCREG_FISEG))
896     xsave.ctrl64.fpu_ip = tc->readMiscRegNoEffect(MISCREG_FIOFF);
898     if (tc->readMiscRegNoEffect(MISCREG_FOSEG))
901     xsave.ctrl64.fpu_dp = tc->readMiscRegNoEffect(MISCREG_FOOFF);
927         e.data = tc->readMiscReg(msrMap.at(*it));
968     tc->setMiscReg(MISCREG_M5_REG, 0);
975 #define APPLY_IREG(kreg, mreg) tc->setIntReg(mreg, regs.kreg)
981     tc->pcState(PCState(regs.rip + sregs.cs.base));
985     X86ISA::setRFlags(tc, regs.rflags);
990 setContextSegment(ThreadContext *tc, const struct kvm_segment &kvm_seg,
1008     tc->setMiscReg(MISCREG_SEG_BASE(index), kvm_seg.base);
1009     tc->setMiscReg(MISCREG_SEG_LIMIT(index), kvm_seg.limit);
1010     tc->setMiscReg(MISCREG_SEG_SEL(index), kvm_seg.selector);
1011     tc->setMiscReg(MISCREG_SEG_ATTR(index), attr);
1015 setContextSegment(ThreadContext *tc, const struct kvm_dtable &kvm_dtable,
1021     tc->setMiscReg(MISCREG_SEG_BASE(index), kvm_dtable.base);
1022     tc->setMiscReg(MISCREG_SEG_LIMIT(index), kvm_dtable.limit);
1031 #define APPLY_SREG(kreg, mreg) tc->setMiscRegNoEffect(mreg, sregs.kreg)
1032 #define APPLY_SEGMENT(kreg, idx) setContextSegment(tc, sregs.kreg, idx)
1033 #define APPLY_DTABLE(kreg, idx) setContextSegment(tc, sregs.kreg, idx)
1044 updateThreadContextFPUCommon(ThreadContext *tc, const T &fpu)
1053         tc->setFloatReg(FLOATREG_FPR(reg_idx), floatToBits64(value));
1058     tc->setMiscRegNoEffect(MISCREG_X87_TOP, top);
1059     tc->setMiscRegNoEffect(MISCREG_MXCSR, fpu.mxcsr);
1060     tc->setMiscRegNoEffect(MISCREG_FCW, fpu.fcw);
1061     tc->setMiscRegNoEffect(MISCREG_FSW, fpu.fsw);
1065     tc->setMiscRegNoEffect(MISCREG_FTW, ftw);
1066     tc->setMiscRegNoEffect(MISCREG_FTAG, ftw);
1068     tc->setMiscRegNoEffect(MISCREG_FOP, fpu.last_opcode);
1071         tc->setFloatReg(FLOATREG_XMM_LOW(i), *(uint64_t *)&fpu.xmm[i][0]);
1072         tc->setFloatReg(FLOATREG_XMM_HIGH(i), *(uint64_t *)&fpu.xmm[i][8]);
1079     updateThreadContextFPUCommon(tc, fpu);
1081     tc->setMiscRegNoEffect(MISCREG_FISEG, 0);
1082     tc->setMiscRegNoEffect(MISCREG_FIOFF, fpu.last_ip);
1083     tc->setMiscRegNoEffect(MISCREG_FOSEG, 0);
1084     tc->setMiscRegNoEffect(MISCREG_FOOFF, fpu.last_dp);
1092     updateThreadContextFPUCommon(tc, xsave);
1094     tc->setMiscRegNoEffect(MISCREG_FISEG, 0);
1095     tc->setMiscRegNoEffect(MISCREG_FIOFF, xsave.ctrl64.fpu_ip);
1096     tc->setMiscRegNoEffect(MISCREG_FOSEG, 0);
1097     tc->setMiscRegNoEffect(MISCREG_FOOFF, xsave.ctrl64.fpu_dp);
1126         tc->setMiscReg(X86ISA::msrMap.at(entry->index), entry->data);
1144         fault = interrupts[0]->getInterrupt(tc);
1145         interrupts[0]->updateIntrInfo(tc);
1154         fault.get()->invoke(tc);
1165         fault.get()->invoke(tc);
1201             if (interrupts[0]->checkInterrupts(tc)) {
1262     kvm_run.apic_base = tc->readMiscReg(MISCREG_APIC_BASE);
1263     kvm_run.cr8 = tc->readMiscReg(MISCREG_CR8);
1267     tc->setMiscReg(MISCREG_APIC_BASE, kvm_run.apic_base);
1268     kvm_run.cr8 = tc->readMiscReg(MISCREG_CR8);
1299         tc->setMiscReg(miscreg, *data);
1301         *data = tc->readMiscRegNoEffect(miscreg);
1334         Addr pciConfigAddr(tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS));
1354         io_req->setContext(tc->contextId());
1434     X86ISA::doCpuid(tc, 0x0, 0, func0);
1439         X86ISA::doCpuid(tc, function, idx, cpuid);
1445     X86ISA::doCpuid(tc, 0x80000000, 0, efunc0);
1450         X86ISA::doCpuid(tc, function, idx, cpuid);