Lines Matching refs:inform

172     inform("KVM register state:\n");
175 inform("\t" # kreg ": 0x%llx\n", regs.kreg)
181 inform("\trip: 0x%llx\n", regs.rip);
182 inform("\trflags: 0x%llx\n", regs.rflags);
188 inform("\t%s: @0x%llx+%x [sel: 0x%x, type: 0x%x]\n"
198 inform("\t%s: @0x%llx+%x\n",
206 inform("\t" # kreg ": 0x%llx\n", sregs.kreg);
212 inform("Special registers:\n");
217 inform("Interrupt Bitmap:");
219 inform(" 0x%.8x", sregs.interrupt_bitmap[i / 64]);
230 inform("KVM debug state:\n");
233 inform("\t" # kreg ": 0x%llx\n", regs.kreg)
239 inform("\tflags: 0x%llx\n", regs.flags);
246 inform("\tlast_ip: 0x%x\n", xs.ctrl64.fpu_ip);
247 inform("\tlast_dp: 0x%x\n", xs.ctrl64.fpu_dp);
248 inform("\tmxcsr_mask: 0x%x\n", xs.mxcsr_mask);
254 inform("\tlast_ip: 0x%x\n", fpu.last_ip);
255 inform("\tlast_dp: 0x%x\n", fpu.last_dp);
263 inform("\tfcw: 0x%x\n", fpu.fcw);
265 inform("\tfsw: 0x%x (top: %i, "
285 inform("\tftwx: 0x%x\n", fpu.ftwx);
286 inform("\tlast_opcode: 0x%x\n", fpu.last_opcode);
288 inform("\tmxcsr: 0x%x\n", fpu.mxcsr);
289 inform("\tFP Stack:\n");
297 inform("\t\tST%i/%i: 0x%s (%f)%s\n", i, reg_idx,
300 inform("\tXMM registers:\n");
305 inform("\t\t%i: 0x%s\n", i, hex);
312 inform("FPU registers:\n");
319 inform("FPU registers (XSave):\n");
326 inform("MSRs:\n");
331 inform("\t0x%x: 0x%x\n", e.index, e.data);
338 inform("KVM XCR registers:\n");
340 inform("\tFlags: 0x%x\n", regs.flags);
342 inform("\tXCR[0x%x]: 0x%x\n",
351 inform("vCPU events:\n");
353 inform("\tException: [inj: %i, nr: %i, has_ec: %i, ec: %i]\n",
357 inform("\tInterrupt: [inj: %i, nr: %i, soft: %i]\n",
361 inform("\tNMI: [inj: %i, pending: %i, masked: %i]\n",
365 inform("\tSIPI vector: 0x%x\n", events.sipi_vector);
366 inform("\tFlags: 0x%x\n", events.flags);
618 inform("Debug registers not supported by kernel.\n");
630 inform("XCRs not supported by kernel.\n");
642 inform("XSave not supported by kernel.\n");