cpu/kvm/x86_cpu.cc

252 dumpFpuSpec(const struct kvm_fpu &fpu)
254     inform("\tlast_ip: 0x%x\n", fpu.last_ip);
255     inform("\tlast_dp: 0x%x\n", fpu.last_dp);
260 dumpFpuCommon(const T &fpu)
262     const unsigned top((fpu.fsw >> 11) & 0x7);
263     inform("\tfcw: 0x%x\n", fpu.fcw);
267            fpu.fsw, top,
269            (fpu.fsw & CC0Bit) ? "C0" : "",
270            (fpu.fsw & CC1Bit) ? "C1" : "",
271            (fpu.fsw & CC2Bit) ? "C2" : "",
272            (fpu.fsw & CC3Bit) ? "C3" : "",
274            (fpu.fsw & IEBit) ? "I" : "",
275            (fpu.fsw & DEBit) ? "D" : "",
276            (fpu.fsw & ZEBit) ? "Z" : "",
277            (fpu.fsw & OEBit) ? "O" : "",
278            (fpu.fsw & UEBit) ? "U" : "",
279            (fpu.fsw & PEBit) ? "P" : "",
281            (fpu.fsw & StackFaultBit) ? "SF " : "",
282            (fpu.fsw & ErrSummaryBit) ? "ES " : "",
283            (fpu.fsw & BusyBit) ? "BUSY " : ""
285     inform("\tftwx: 0x%x\n", fpu.ftwx);
286     inform("\tlast_opcode: 0x%x\n", fpu.last_opcode);
287     dumpFpuSpec(fpu);
288     inform("\tmxcsr: 0x%x\n", fpu.mxcsr);
292         const bool empty(!((fpu.ftwx >> reg_idx) & 0x1));
293         const double value(X86ISA::loadFloat80(fpu.fpr[i]));
296             snprintf(&hex[j*2], 3, "%.2x", fpu.fpr[i][j]);
304             snprintf(&hex[j*2], 3, "%.2x", fpu.xmm[i][j]);
310 dumpKvm(const struct kvm_fpu &fpu)
313     dumpFpuCommon(fpu);
587     struct kvm_fpu fpu;
588     getFPUState(fpu);
589     dumpKvm(fpu);
824 updateKvmStateFPUCommon(ThreadContext *tc, T &fpu)
826     fpu.mxcsr = tc->readMiscRegNoEffect(MISCREG_MXCSR);
827     fpu.fcw = tc->readMiscRegNoEffect(MISCREG_FCW);
830     fpu.fsw = tc->readMiscReg(MISCREG_FSW);
833     fpu.ftwx = X86ISA::convX87TagsToXTags(ftw);
835     fpu.last_opcode = tc->readMiscRegNoEffect(MISCREG_FOP);
837     const unsigned top((fpu.fsw >> 11) & 0x7);
844         X86ISA::storeFloat80(fpu.fpr[i], value);
850         *(uint64_t *)&fpu.xmm[i][0] =
852         *(uint64_t *)&fpu.xmm[i][8] =
860     struct kvm_fpu fpu;
864     memset(&fpu, 0, sizeof(fpu));
866     updateKvmStateFPUCommon(tc, fpu);
871     fpu.last_ip = tc->readMiscRegNoEffect(MISCREG_FIOFF);
876     fpu.last_dp = tc->readMiscRegNoEffect(MISCREG_FOOFF);
878     setFPUState(fpu);
958         struct kvm_fpu fpu;
959         getFPUState(fpu);
961         updateThreadContextFPU(fpu);
1044 updateThreadContextFPUCommon(ThreadContext *tc, const T &fpu)
1046     const unsigned top((fpu.fsw >> 11) & 0x7);
1050         const double value(X86ISA::loadFloat80(fpu.fpr[i]));
1059     tc->setMiscRegNoEffect(MISCREG_MXCSR, fpu.mxcsr);
1060     tc->setMiscRegNoEffect(MISCREG_FCW, fpu.fcw);
1061     tc->setMiscRegNoEffect(MISCREG_FSW, fpu.fsw);
1063     uint64_t ftw(convX87XTagsToTags(fpu.ftwx));
1068     tc->setMiscRegNoEffect(MISCREG_FOP, fpu.last_opcode);
1071         tc->setFloatReg(FLOATREG_XMM_LOW(i), *(uint64_t *)&fpu.xmm[i][0]);
1072         tc->setFloatReg(FLOATREG_XMM_HIGH(i), *(uint64_t *)&fpu.xmm[i][8]);
1077 X86KvmCPU::updateThreadContextFPU(const struct kvm_fpu &fpu)
1079     updateThreadContextFPUCommon(tc, fpu);
1082     tc->setMiscRegNoEffect(MISCREG_FIOFF, fpu.last_ip);
1084     tc->setMiscRegNoEffect(MISCREG_FOOFF, fpu.last_dp);