Lines Matching defs:val

270     setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
274 return thread->setVecLane(reg, val);
278 const LaneData<LaneSize::Byte>& val) override
280 setVecLaneOperandT(si, idx, val);
284 const LaneData<LaneSize::TwoByte>& val) override
286 setVecLaneOperandT(si, idx, val);
290 const LaneData<LaneSize::FourByte>& val) override
292 setVecLaneOperandT(si, idx, val);
296 const LaneData<LaneSize::EightByte>& val) override
298 setVecLaneOperandT(si, idx, val);
366 setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
370 thread->setIntReg(reg.index(), val);
371 setScalarResult(val);
375 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
379 thread->setFloatReg(reg.index(), val);
380 setScalarResult(val);
384 setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
388 thread->setCCReg(reg.index(), val);
389 setScalarResult((uint64_t)val);
394 const VecRegContainer& val) override
398 thread->setVecReg(reg, val);
399 setVecResult(val);
404 const VecElem val) override
408 thread->setVecElem(reg, val);
409 setVecElemResult(val);
413 const VecPredRegContainer& val) override
417 thread->setVecPredReg(reg, val);
418 setVecPredResult(val);
424 setPredicate(bool val) override
426 thread->setPredicate(val);
436 setMemAccPredicate(bool val) override
438 thread->setMemAccPredicate(val);
443 pcState(const TheISA::PCState &val) override
446 val, thread->pcState());
447 thread->pcState(val);
467 setMiscRegNoEffect(int misc_reg, RegVal val)
472 return thread->setMiscRegNoEffect(misc_reg, val);
476 setMiscReg(int misc_reg, RegVal val) override
481 return thread->setMiscReg(misc_reg, val);
493 setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
497 return this->setMiscReg(reg.index(), val);
503 recordPCChange(const TheISA::PCState &val)
506 newPCState = val;