cpu/checker/cpu.hh

194         const RegId& reg = si->srcRegIdx(idx);
195         assert(reg.isIntReg());
196         return thread->readIntReg(reg.index());
202         const RegId& reg = si->srcRegIdx(idx);
203         assert(reg.isFloatReg());
204         return thread->readFloatReg(reg.index());
213         const RegId& reg = si->srcRegIdx(idx);
214         assert(reg.isVecReg());
215         return thread->readVecReg(reg);
224         const RegId& reg = si->destRegIdx(idx);
225         assert(reg.isVecReg());
226         return thread->getWritableVecReg(reg);
235         const RegId& reg = si->destRegIdx(idx);
236         assert(reg.isVecReg());
237         return thread->readVec8BitLaneReg(reg);
244         const RegId& reg = si->destRegIdx(idx);
245         assert(reg.isVecReg());
246         return thread->readVec16BitLaneReg(reg);
253         const RegId& reg = si->destRegIdx(idx);
254         assert(reg.isVecReg());
255         return thread->readVec32BitLaneReg(reg);
262         const RegId& reg = si->destRegIdx(idx);
263         assert(reg.isVecReg());
264         return thread->readVec64BitLaneReg(reg);
272         const RegId& reg = si->destRegIdx(idx);
273         assert(reg.isVecReg());
274         return thread->setVecLane(reg, val);
305         const RegId& reg = si->srcRegIdx(idx);
306         return thread->readVecElem(reg);
312         const RegId& reg = si->srcRegIdx(idx);
313         assert(reg.isVecPredReg());
314         return thread->readVecPredReg(reg);
320         const RegId& reg = si->destRegIdx(idx);
321         assert(reg.isVecPredReg());
322         return thread->getWritableVecPredReg(reg);
328         const RegId& reg = si->srcRegIdx(idx);
329         assert(reg.isCCReg());
330         return thread->readCCReg(reg.index());
368         const RegId& reg = si->destRegIdx(idx);
369         assert(reg.isIntReg());
370         thread->setIntReg(reg.index(), val);
377         const RegId& reg = si->destRegIdx(idx);
378         assert(reg.isFloatReg());
379         thread->setFloatReg(reg.index(), val);
386         const RegId& reg = si->destRegIdx(idx);
387         assert(reg.isCCReg());
388         thread->setCCReg(reg.index(), val);
396         const RegId& reg = si->destRegIdx(idx);
397         assert(reg.isVecReg());
398         thread->setVecReg(reg, val);
406         const RegId& reg = si->destRegIdx(idx);
407         assert(reg.isVecElem());
408         thread->setVecElem(reg, val);
415         const RegId& reg = si->destRegIdx(idx);
416         assert(reg.isVecPredReg());
417         thread->setVecPredReg(reg, val);
469         DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n",
478         DPRINTF(Checker, "Setting misc reg %d with effect to check later\n",
487         const RegId& reg = si->srcRegIdx(idx);
488         assert(reg.isMiscReg());
489         return thread->readMiscReg(reg.index());
495         const RegId& reg = si->destRegIdx(idx);
496         assert(reg.isMiscReg());
497         return this->setMiscReg(reg.index(), val);