arch/x86/utility.cc

53 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
68         return tc->readIntReg(int_reg_map[number]);
74 void initCPU(ThreadContext *tc, int cpuId)
80     init.invoke(tc);
82     PCState pc = tc->pcState();
85     tc->pcState(pc);
91         tc->setIntReg(INTREG_MICRO(index), 0);
95         tc->setIntReg(INTREG_IMPLICIT(index), 0);
101     tc->setIntReg(INTREG_RAX, 0);
103     tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL);
104     tc->setMiscReg(MISCREG_CR8, 0);
108     tc->setMiscReg(MISCREG_MTRRCAP, 0x0508);
110         tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0);
111         tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0);
113     tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0);
114     tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0);
115     tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0);
116     tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0);
117     tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0);
118     tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0);
119     tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0);
120     tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0);
121     tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0);
122     tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0);
123     tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0);
125     tc->setMiscReg(MISCREG_DEF_TYPE, 0);
127     tc->setMiscReg(MISCREG_MCG_CAP, 0x104);
128     tc->setMiscReg(MISCREG_MCG_STATUS, 0);
129     tc->setMiscReg(MISCREG_MCG_CTL, 0);
132         tc->setMiscReg(MISCREG_MC_CTL(i), 0);
133         tc->setMiscReg(MISCREG_MC_STATUS(i), 0);
134         tc->setMiscReg(MISCREG_MC_ADDR(i), 0);
135         tc->setMiscReg(MISCREG_MC_MISC(i), 0);
138     tc->setMiscReg(MISCREG_TSC, 0);
139     tc->setMiscReg(MISCREG_TSC_AUX, 0);
142         tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0);
143         tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0);
146     tc->setMiscReg(MISCREG_STAR, 0);
147     tc->setMiscReg(MISCREG_LSTAR, 0);
148     tc->setMiscReg(MISCREG_CSTAR, 0);
150     tc->setMiscReg(MISCREG_SF_MASK, 0);
152     tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0);
154     tc->setMiscReg(MISCREG_SYSENTER_CS, 0);
155     tc->setMiscReg(MISCREG_SYSENTER_ESP, 0);
156     tc->setMiscReg(MISCREG_SYSENTER_EIP, 0);
158     tc->setMiscReg(MISCREG_PAT, 0x0007040600070406ULL);
160     tc->setMiscReg(MISCREG_SYSCFG, 0x20601);
162     tc->setMiscReg(MISCREG_IORR_BASE0, 0);
163     tc->setMiscReg(MISCREG_IORR_BASE1, 0);
165     tc->setMiscReg(MISCREG_IORR_MASK0, 0);
166     tc->setMiscReg(MISCREG_IORR_MASK1, 0);
168     tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000);
169     tc->setMiscReg(MISCREG_TOP_MEM2, 0x0);
171     tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0);
172     tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0);
173     tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0);
174     tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0);
175     tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0);
183     tc->setMiscReg(MISCREG_APIC_BASE, lApicBase);
186             tc->getCpuPtr()->getInterruptController(0));
195     tc->setMiscReg(MISCREG_VM_CR, 0);
196     tc->setMiscReg(MISCREG_IGNNE, 0);
197     tc->setMiscReg(MISCREG_SMM_CTL, 0);
198     tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
201 void startupCPU(ThreadContext *tc, int cpuId)
204         tc->activate();
209         tc->suspend();
251 skipFunction(ThreadContext *tc)
257 getRFlags(ThreadContext *tc)
259     const uint64_t ncc_flags(tc->readMiscRegNoEffect(MISCREG_RFLAGS));
260     const uint64_t cc_flags(tc->readCCReg(X86ISA::CCREG_ZAPS));
261     const uint64_t cfof_bits(tc->readCCReg(X86ISA::CCREG_CFOF));
262     const uint64_t df_bit(tc->readCCReg(X86ISA::CCREG_DF));
273 setRFlags(ThreadContext *tc, uint64_t val)
275     tc->setCCReg(X86ISA::CCREG_ZAPS, val & ccFlagMask);
276     tc->setCCReg(X86ISA::CCREG_CFOF, val & cfofMask);
277     tc->setCCReg(X86ISA::CCREG_DF, val & DFBit);
280     tc->setCCReg(X86ISA::CCREG_ECF, 0);
281     tc->setCCReg(X86ISA::CCREG_EZF, 0);
285     tc->setMiscReg(MISCREG_RFLAGS, val & ~(ccFlagMask | cfofMask | DFBit));