Lines Matching defs:req

173 TLB::translateInt(const RequestPtr &req, ThreadContext *tc)
176 Addr vaddr = req->getVaddr();
182 req->setFlags(Request::MMAPPED_IPR);
191 req->setPaddr((Addr)regNum * sizeof(RegVal));
201 if (IOPort == 0xCF8 && req->getSize() == 4) {
202 req->setFlags(Request::MMAPPED_IPR);
203 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(RegVal));
205 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
209 req->setPaddr(PhysAddrPrefixPciConfig |
213 req->setPaddr(PhysAddrPrefixIO | IOPort);
216 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
217 req->setPaddr(PhysAddrPrefixIO | IOPort);
227 TLB::finalizePhysical(const RequestPtr &req,
230 Addr paddr = req->getPaddr();
235 req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR |
237 req->setPaddr(GenericISA::iprAddressPseudoInst((paddr >> 8) & 0xFF,
255 if (req->getSize() != (32/8))
259 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
260 req->setPaddr(x86LocalAPICAddress(tc->contextId(),
269 TLB::translate(const RequestPtr &req,
273 Request::Flags flags = req->getFlags();
282 return translateInt(req, tc);
285 Addr vaddr = req->getVaddr();
318 Addr endOffset = offset + req->getSize() - 1;
352 Fault fault = walker->start(tc, translation, req, mode);
410 req->setPaddr(paddr);
412 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
417 req->setPaddr(vaddr);
423 req->setPaddr(vaddr);
426 return finalizePhysical(req, tc, mode);
430 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
433 return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
437 TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
443 TLB::translate(req, tc, translation, mode, delayedResponse, true);
445 translation->finish(fault, req, tc, mode);