arch/x86/tlb.cc

54 #include "debug/TLB.hh"
62 TLB::TLB(const Params *p)
79 TLB::evictLRU()
97 TLB::insert(Addr vpn, const TlbEntry &entry)
121 TLB::lookup(Addr va, bool update_lru)
130 TLB::flushAll()
132     DPRINTF(TLB, "Invalidating all entries.\n");
143 TLB::setConfigAddress(uint32_t addr)
149 TLB::flushNonGlobal()
151     DPRINTF(TLB, "Invalidating all non global entries.\n");
162 TLB::demapPage(Addr va, uint64_t asn)
173 TLB::translateInt(const RequestPtr &req, ThreadContext *tc)
175     DPRINTF(TLB, "Addresses references internal memory.\n");
227 TLB::finalizePhysical(const RequestPtr &req,
269 TLB::translate(const RequestPtr &req,
286     DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
292         DPRINTF(TLB, "In protected mode.\n");
295             DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
320                 DPRINTF(TLB, "Checking an expand down segment.\n");
334             DPRINTF(TLB, "Paging enabled.\n");
343                 DPRINTF(TLB, "Handling a TLB miss for "
376                         DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
383                     DPRINTF(TLB, "Miss was serviced.\n");
387             DPRINTF(TLB, "Entry found with paddr %#x, "
395                 // The page must have been present to get into the TLB in
409             DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
415             DPRINTF(TLB, "Paging disabled.\n");
416             DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
421         DPRINTF(TLB, "In real mode.\n");
422         DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
430 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
433     return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
437 TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
443         TLB::translate(req, tc, translation, mode, delayedResponse, true);
451 TLB::getWalker()
457 TLB::regStats()
463         .desc("TLB accesses on read requests");
467         .desc("TLB accesses on write requests");
471         .desc("TLB misses on read requests");
475         .desc("TLB misses on write requests");
480 TLB::serialize(CheckpointOut &cp) const
495 TLB::unserialize(CheckpointIn &cp)
501         fatal("TLB size less than the one in checkpoint!");
517 TLB::getTableWalkerPort()
524 X86ISA::TLB *
527     return new X86ISA::TLB(this);