arch/x86/faults.cc

55     void X86FaultBase::invoke(ThreadContext * tc, const StaticInstPtr &inst)
58             FaultBase::invoke(tc, inst);
62         PCState pcState = tc->pcState();
67         HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
78         tc->setIntReg(INTREG_MICRO(1), vector);
79         tc->setIntReg(INTREG_MICRO(7), pc);
90             tc->setIntReg(INTREG_MICRO(15), errorCode);
94         tc->pcState(pcState);
109     void X86Trap::invoke(ThreadContext * tc, const StaticInstPtr &inst)
111         X86FaultBase::invoke(tc);
117         PCState pc = tc->pcState();
121     void X86Abort::invoke(ThreadContext * tc, const StaticInstPtr &inst)
127     InvalidOpcode::invoke(ThreadContext * tc, const StaticInstPtr &inst)
130             X86Fault::invoke(tc, inst);
137     void PageFault::invoke(ThreadContext * tc, const StaticInstPtr &inst)
141             tc->getITBPtr()->demapPage(addr, 0);
142             tc->getDTBPtr()->demapPage(addr, 0);
143             HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
144             X86FaultBase::invoke(tc);
152                 tc->setMiscReg(MISCREG_CR2, addr);
154                 tc->setMiscReg(MISCREG_CR2, (uint32_t)addr);
171                       modeStr, addr, tc->pcState().pc(),
172                       inst->disassemble(tc->pcState().pc(), debugSymbolTable));
186     InitInterrupt::invoke(ThreadContext *tc, const StaticInstPtr &inst)
191             tc->setIntReg(index, 0);
194         CR0 cr0 = tc->readMiscReg(MISCREG_CR0);
198         tc->setMiscReg(MISCREG_CR0, newCR0);
199         tc->setMiscReg(MISCREG_CR2, 0);
200         tc->setMiscReg(MISCREG_CR3, 0);
201         tc->setMiscReg(MISCREG_CR4, 0);
203         tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002ULL);
205         tc->setMiscReg(MISCREG_EFER, 0);
222             tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
223             tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
224             tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), 0);
225             tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
226             tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr);
243         tc->setMiscReg(MISCREG_CS, 0xf000);
244         tc->setMiscReg(MISCREG_CS_BASE,
246         tc->setMiscReg(MISCREG_CS_EFF_BASE,
249         tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
250         tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
252         PCState pc(0x000000000000fff0ULL + tc->readMiscReg(MISCREG_CS_BASE));
253         tc->pcState(pc);
255         tc->setMiscReg(MISCREG_TSG_BASE, 0);
256         tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
258         tc->setMiscReg(MISCREG_IDTR_BASE, 0);
259         tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
264         tc->setMiscReg(MISCREG_TSL, 0);
265         tc->setMiscReg(MISCREG_TSL_BASE, 0);
266         tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff);
267         tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr);
272         tc->setMiscReg(MISCREG_TR, 0);
273         tc->setMiscReg(MISCREG_TR_BASE, 0);
274         tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
275         tc->setMiscReg(MISCREG_TR_ATTR, trAttr);
280         tc->setIntReg(INTREG_RDX, 0);
282         tc->setMiscReg(MISCREG_DR0, 0);
283         tc->setMiscReg(MISCREG_DR1, 0);
284         tc->setMiscReg(MISCREG_DR2, 0);
285         tc->setMiscReg(MISCREG_DR3, 0);
287         tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0ULL);
288         tc->setMiscReg(MISCREG_DR7, 0x0000000000000400ULL);
290         tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
293         tc->setMiscReg(MISCREG_FTW, 0xFFFF);
296         tc->setMiscReg(MISCREG_M5_REG, 0);
300         tc->pcState(pc);
304     StartupInterrupt::invoke(ThreadContext *tc, const StaticInstPtr &inst)
307         HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG);
313         tc->setMiscReg(MISCREG_CS, vector << 8);
314         tc->setMiscReg(MISCREG_CS_BASE, vector << 12);
315         tc->setMiscReg(MISCREG_CS_EFF_BASE, vector << 12);
317         tc->setMiscReg(MISCREG_CS_LIMIT, 0xffff);
319         tc->pcState(tc->readMiscReg(MISCREG_CS_BASE));