arch/sparc/utility.cc

68 copyMiscRegs(ThreadContext *src, ThreadContext *dest)
76         dest->setMiscRegNoEffect(MISCREG_TL, i);
78         dest->setMiscRegNoEffect(MISCREG_TT,
80         dest->setMiscRegNoEffect(MISCREG_TPC,
82         dest->setMiscRegNoEffect(MISCREG_TNPC,
84         dest->setMiscRegNoEffect(MISCREG_TSTATE,
89     dest->setMiscRegNoEffect(MISCREG_TL, tl);
94 //    dest->setMiscRegNoEffect(MISCREG_Y,
96 //    dest->setMiscRegNoEffect(MISCREG_CCR,
98     dest->setMiscReg(MISCREG_ASI,
100     dest->setMiscRegNoEffect(MISCREG_TICK,
102     dest->setMiscRegNoEffect(MISCREG_FPRS,
104     dest->setMiscRegNoEffect(MISCREG_SOFTINT,
106     dest->setMiscRegNoEffect(MISCREG_TICK_CMPR,
108     dest->setMiscRegNoEffect(MISCREG_STICK,
110     dest->setMiscRegNoEffect(MISCREG_STICK_CMPR,
114     dest->setMiscRegNoEffect(MISCREG_TICK,
116     dest->setMiscRegNoEffect(MISCREG_TBA,
118     dest->setMiscRegNoEffect(MISCREG_PSTATE,
120     dest->setMiscRegNoEffect(MISCREG_PIL,
122     dest->setMiscReg(MISCREG_CWP,
124 //    dest->setMiscRegNoEffect(MISCREG_CANSAVE,
126 //    dest->setMiscRegNoEffect(MISCREG_CANRESTORE,
128 //    dest->setMiscRegNoEffect(MISCREG_OTHERWIN,
130 //    dest->setMiscRegNoEffect(MISCREG_CLEANWIN,
132 //    dest->setMiscRegNoEffect(MISCREG_WSTATE,
134     dest->setMiscReg(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL));
137     dest->setMiscRegNoEffect(MISCREG_HPSTATE,
139     dest->setMiscRegNoEffect(MISCREG_HINTP,
141     dest->setMiscRegNoEffect(MISCREG_HTBA,
143     dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
145     dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR,
149     dest->setMiscRegNoEffect(MISCREG_FSR,
153     dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
157     dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT,
159     dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT,
161     dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID,
163     dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL,
167     dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0,
169     dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1,
171     dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2,
173     dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3,
175     dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4,
177     dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5,
179     dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6,
181     dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7,
185     dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD,
187     dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL,
189     dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD,
191     dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL,
193     dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD,
195     dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL,
197     dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD,
199     dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL,
204 copyRegs(ThreadContext *src, ThreadContext *dest)
212         dest->setMiscReg(MISCREG_GL, x);
215             dest->setIntReg(y, src->readIntReg(y));
220          dest->setMiscReg(MISCREG_CWP, x);
222              dest->setIntReg(y, src->readIntReg(y));
226         dest->setIntReg(y, src->readIntReg(y));
235         dest->setFloatReg(i, src->readFloatReg(i));
242     copyMiscRegs(src, dest);
245     dest->pcState(src->pcState());