arch/sparc/tlb.cc

97 TLB::insert(Addr va, int partition_id, int context_id, bool real,
106     va &= ~(PTE.size()-1);
107  /*   tr.va = va;
115         "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
116         va, PTE.paddr(), partition_id, context_id, (int)real, entry);
122             tlb[x].range.va < va + PTE.size() - 1 &&
123             tlb[x].range.va + tlb[x].range.size >= va &&
174     new_entry->range.va = va;
198 TLB::lookup(Addr va, int partition_id, bool real, int context_id,
205     DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
206             va, partition_id, context_id, real);
208     tr.va = va;
250                    tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
256 TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
261     DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
262             va, partition_id, context_id, real);
267     tr.va = va;
365     tag |= tlb[entry].range.va;
373 TLB::validVirtualAddress(Addr va, bool am)
377     if (va >= StartVAddrHole && va <= EndVAddrHole)
400 TLB::writeTagAccess(Addr va, int context)
402     DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
403             va, context, mbits(va, 63,13) | mbits(context,12,0));
405     tag_access = mbits(va, 63,13) | mbits(context,12,0);
428     DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
434             if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) &&
435                 cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) {
548     DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
572                 Addr ce_va = ce->range.va;
587                 Addr ce_va = ce->range.va;
863     Addr va = pkt->getAddr();
874         assert(va == 0);
878         switch (va) {
891                     (va >> 4) - 0x3c));
894         assert(va == 0);
898         assert(va == 0);
902         assert(va == 0);
906         assert(va == 0);
910         assert(va == 0);
914         assert(va == 0);
918         assert(va == 0);
922         assert(va == 0);
926         assert(va == 0);
930         assert(va == 0);
934         assert(va == 0);
938         assert(va == 0);
946         pkt->setBE(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
949         switch (va) {
965         switch (va) {
1038         panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1039             (uint32_t)asi, va);
1049     Addr va = pkt->getAddr();
1064          (uint32_t)asi, va, data);
1070         assert(va == 0);
1074         switch (va) {
1088                     (va >> 4) - 0x3c, data);
1091         assert(va == 0);
1095         assert(va == 0);
1099         assert(va == 0);
1103         assert(va == 0);
1107         assert(va == 0);
1111         assert(va == 0);
1115         assert(va == 0);
1119         assert(va == 0);
1123         assert(va == 0);
1127         assert(va == 0);
1131         assert(va == 0);
1135         assert(va == 0);
1144         tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1147         switch (va) {
1160         entry_insert = bits(va, 8,3);
1163         assert(entry_insert != -1 || mbits(va,10,9) == va);
1168         real_insert = bits(va, 9,9);
1169         pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1175         entry_insert = bits(va, 8,3);
1178         assert(entry_insert != -1 || mbits(va,10,9) == va);
1183         real_insert = bits(va, 9,9);
1184         pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1193         switch (bits(va,5,4)) {
1207         switch (bits(va,7,6)) {
1210                 itb->demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1224         switch (va) {
1243         switch (bits(va,5,4)) {
1257         switch (bits(va,7,6)) {
1260                 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1292         panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",