Lines Matching defs:req

419 TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
423 Addr vaddr = req->getVaddr();
426 assert(req->getArchFlags() == ASI_IMPLICIT);
429 vaddr, req->getSize());
436 req->setPaddr(cacheEntry[0]->pte.translate(vaddr));
440 req->setPaddr(vaddr & PAddrImplMask);
476 req->setPaddr(vaddr & PAddrImplMask);
511 req->getVaddr());
527 req->setPaddr(e->pte.translate(vaddr));
528 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
533 TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
540 Addr vaddr = req->getVaddr();
541 Addr size = req->getSize();
543 asi = (ASI)req->getArchFlags();
561 req->setPaddr(vaddr & PAddrImplMask);
576 req->setPaddr(ce->pte.translate(vaddr));
578 req->setFlags(
581 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
591 req->setPaddr(ce->pte.translate(vaddr));
593 req->setFlags(
596 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
712 req->setPaddr(vaddr & PAddrImplMask);
728 req->getVaddr());
758 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
776 req->setPaddr(e->pte.translate(vaddr));
777 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
831 req->setFlags(Request::MMAPPED_IPR);
832 req->setPaddr(req->getVaddr());
837 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
840 return translateInst(req, tc);
842 return translateData(req, tc, mode == Write);
846 TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
850 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
854 TLB::finalizePhysical(const RequestPtr &req,
864 ASI asi = (ASI)pkt->req->getArchFlags();
868 (uint32_t)pkt->req->getArchFlags(), pkt->getAddr());
1050 ASI asi = (ASI)pkt->req->getArchFlags();
1293 (uint32_t)pkt->req->getArchFlags(), pkt->getAddr(), data);