arch/sparc/faults.cc

282 enterREDState(ThreadContext *tc)
286     HPSTATE hpstate= tc->readMiscRegNoEffect(MISCREG_HPSTATE);
289     tc->setMiscReg(MISCREG_HPSTATE, hpstate);
292     PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
294     tc->setMiscReg(MISCREG_PSTATE, pstate);
303 doREDFault(ThreadContext *tc, TrapType tt)
305     RegVal TL = tc->readMiscRegNoEffect(MISCREG_TL);
306     RegVal TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
307     PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
308     HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
309     RegVal CCR = tc->readIntReg(NumIntArchRegs + 2);
310     RegVal ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
311     RegVal CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
312     RegVal CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3);
313     RegVal GL = tc->readMiscRegNoEffect(MISCREG_GL);
314     PCState pc = tc->pcState();
332     tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
335     tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask);
337     tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask);
340     tc->setMiscRegNoEffect(MISCREG_HTSTATE, hpstate);
343     tc->setMiscRegNoEffect(MISCREG_TT, tt);
346     tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL));
352     tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate);
358     tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate);
372         tc->setMiscReg(MISCREG_CWP, CWP);
382 doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
384     RegVal TL = tc->readMiscRegNoEffect(MISCREG_TL);
385     RegVal TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
386     PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
387     HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
388     RegVal CCR = tc->readIntReg(NumIntArchRegs + 2);
389     RegVal ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
390     RegVal CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
391     RegVal CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
392     RegVal GL = tc->readMiscRegNoEffect(MISCREG_GL);
393     PCState pc = tc->pcState();
397     tc->setMiscRegNoEffect(MISCREG_TL, TL);
415     tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
418     tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask);
420     tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask);
423     tc->setMiscRegNoEffect(MISCREG_HTSTATE, hpstate);
426     tc->setMiscRegNoEffect(MISCREG_TT, tt);
430         tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxPGL));
432         tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxGL));
448         tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate);
453     tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate);
468         tc->setMiscReg(MISCREG_CWP, CWP);
482 getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, RegVal TT)
484     Addr HTBA = tc->readMiscRegNoEffect(MISCREG_HTBA);
490 getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT, RegVal TL)
492     Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA);
500 SparcFaultBase::invoke(ThreadContext * tc, const StaticInstPtr &inst)
502     FaultBase::invoke(tc);
510     RegVal tl = tc->readMiscRegNoEffect(MISCREG_TL);
511     RegVal tt = tc->readMiscRegNoEffect(MISCREG_TT);
512     PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
513     HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
529         doREDFault(tc, tt);
532         enterREDState(tc);
540         doNormalFault(tc, trapType(), true);
541         getHyperVector(tc, PC, NPC, 2);
544         doNormalFault(tc, trapType(), true);
545         getHyperVector(tc, PC, NPC, trapType());
547         doNormalFault(tc, trapType(), false);
548         getPrivVector(tc, PC, NPC, trapType(), tl + 1);
557     tc->pcState(pc);
561 PowerOnReset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
567     tc->setMiscRegNoEffect(MISCREG_TL, MaxTL);
568     tc->setMiscRegNoEffect(MISCREG_TT, trapType());
569     tc->setMiscReg(MISCREG_GL, MaxGL);
574     tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate);
577     HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
582     tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate);
585     tc->setMiscRegNoEffect(MISCREG_TICK, 1ULL << 63);
589     enterREDState(tc);
600     tc->pcState(pc);
608     tc->setMiscRegNoEffect(MISCREG_
624 FastInstructionAccessMMUMiss::invoke(ThreadContext *tc,
628         SparcFaultBase::invoke(tc, inst);
632     Process *p = tc->getProcessPtr();
640     uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
675     dynamic_cast<TLB *>(tc->getITBPtr())->
680 FastDataAccessMMUMiss::invoke(ThreadContext *tc, const StaticInstPtr &inst)
683         SparcFaultBase::invoke(tc, inst);
687     Process *p = tc->getProcessPtr();
697     uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
734     RegVal reg_asi = tc->readMiscRegNoEffect(MISCREG_ASI);
762     dynamic_cast<TLB *>(tc->getDTBPtr())->
767 SpillNNormal::invoke(ThreadContext *tc, const StaticInstPtr &inst)
770         SparcFaultBase::invoke(tc, inst);
774     doNormalFault(tc, trapType(), false);
776     Process *p = tc->getProcessPtr();
782     tc->pcState(sp->readSpillStart());
786 FillNNormal::invoke(ThreadContext *tc, const StaticInstPtr &inst)
789         SparcFaultBase::invoke(tc, inst);
793     doNormalFault(tc, trapType(), false);
795     Process *p = tc->getProcessPtr();
801     tc->pcState(sp->readFillStart());
805 TrapInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst)
808         SparcFaultBase::invoke(tc, inst);
816     Process *p = tc->getProcessPtr();
822     sp->handleTrap(_n, tc, &fault);
826     PCState pc = tc->pcState();
828     tc->pcState(pc);