Lines Matching defs:misc_reg
76 ISA::hpmCounterEnabled(int misc_reg) const
78 int hpmcounter = misc_reg - MISCREG_CYCLE;
99 ISA::readMiscRegNoEffect(int misc_reg) const
101 if (misc_reg > NumMiscRegs || misc_reg < 0) {
103 panic("Illegal CSR index %#x\n", misc_reg);
106 DPRINTF(RiscvMisc, "Reading MiscReg %d: %#llx.\n", misc_reg,
107 miscRegFile[misc_reg]);
108 return miscRegFile[misc_reg];
112 ISA::readMiscReg(int misc_reg, ThreadContext *tc)
114 switch (misc_reg) {
153 if (misc_reg >= MISCREG_HPMCOUNTER03 &&
154 misc_reg <= MISCREG_HPMCOUNTER31) {
155 if (hpmCounterEnabled(misc_reg)) {
157 misc_reg - MISCREG_CYCLE, tc->getCpuPtr()->curCycle());
160 warn("HPM counter %d disabled.\n", misc_reg - MISCREG_CYCLE);
164 return readMiscRegNoEffect(misc_reg);
169 ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
171 if (misc_reg > NumMiscRegs || misc_reg < 0) {
173 panic("Illegal CSR index %#x\n", misc_reg);
175 DPRINTF(RiscvMisc, "Setting MiscReg %d to %#x.\n", misc_reg, val);
176 miscRegFile[misc_reg] = val;
180 ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
182 if (misc_reg >= MISCREG_CYCLE && misc_reg <= MISCREG_HPMCOUNTER31) {
184 warn("Ignoring write to %s.\n", CSRData.at(misc_reg).name);
186 switch (misc_reg) {
194 setMiscRegNoEffect(misc_reg, val);