arch/power/tlb.cc

51 #include "debug/TLB.hh"
62 //  POWER TLB
67 TLB::TLB(const Params *p)
75 TLB::~TLB()
81 // look up an entry in the TLB
83 TLB::lookup(Addr vpn, uint8_t asn) const
106     DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
112 TLB::getEntry(unsigned Index) const
120 TLB::probeEntry(Addr vpn,uint8_t asn) const
148 TLB::checkCacheability(const RequestPtr &req)
160 TLB::insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages)
164         warn("Attempted to write at index (%d) beyond TLB size (%d)",
168         // Update TLB
182 // insert a new TLB entry
184 TLB::insert(Addr addr, PowerISA::PTE &pte)
186     fatal("TLB Insert not yet implemented\n");
190 TLB::flushAll()
192     DPRINTF(TLB, "flushAll\n");
199 TLB::serialize(CheckpointOut &cp) const
211 TLB::unserialize(CheckpointIn &cp)
225 TLB::regStats()
282 TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
286         DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(),
301 TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
313 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
325 TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
333 TLB::finalizePhysical(const RequestPtr &req,
340 TLB::index(bool advance)
350 PowerISA::TLB *
353     return new PowerISA::TLB(this);