arch/mips/isa.cc

170     CoreSpecific cp;
181     procId.coOp = cp.CP0_PRId_CompanyOptions;
182     procId.coId = cp.CP0_PRId_CompanyID;
183     procId.procId = cp.CP0_PRId_ProcessorID;
184     procId.rev = cp.CP0_PRId_Revision;
194     cfg.be = cp.CP0_Config_BE;
195     cfg.at = cp.CP0_Config_AT;
196     cfg.ar = cp.CP0_Config_AR;
197     cfg.mt = cp.CP0_Config_MT;
198     cfg.vi = cp.CP0_Config_VI;
208     cfg1.mmuSize = cp.CP0_Config1_MMU;
209     cfg1.is = cp.CP0_Config1_IS;
210     cfg1.il = cp.CP0_Config1_IL;
211     cfg1.ia = cp.CP0_Config1_IA;
212     cfg1.ds = cp.CP0_Config1_DS;
213     cfg1.dl = cp.CP0_Config1_DL;
214     cfg1.da = cp.CP0_Config1_DA;
215     cfg1.fp = cp.CP0_Config1_FP;
216     cfg1.ep = cp.CP0_Config1_EP;
217     cfg1.wr = cp.CP0_Config1_WR;
218     cfg1.md = cp.CP0_Config1_MD;
219     cfg1.c2 = cp.CP0_Config1_C2;
220     cfg1.pc = cp.CP0_Config1_PC;
221     cfg1.m = cp.CP0_Config1_M;
230     cfg2.tu = cp.CP0_Config2_TU;
231     cfg2.ts = cp.CP0_Config2_TS;
232     cfg2.tl = cp.CP0_Config2_TL;
233     cfg2.ta = cp.CP0_Config2_TA;
234     cfg2.su = cp.CP0_Config2_SU;
235     cfg2.ss = cp.CP0_Config2_SS;
236     cfg2.sl = cp.CP0_Config2_SL;
237     cfg2.sa = cp.CP0_Config2_SA;
238     cfg2.m = cp.CP0_Config2_M;
247     cfg3.dspp = cp.CP0_Config3_DSPP;
248     cfg3.lpa = cp.CP0_Config3_LPA;
249     cfg3.veic = cp.CP0_Config3_VEIC;
250     cfg3.vint = cp.CP0_Config3_VInt;
251     cfg3.sp = cp.CP0_Config3_SP;
252     cfg3.mt = cp.CP0_Config3_MT;
253     cfg3.sm = cp.CP0_Config3_SM;
254     cfg3.tl = cp.CP0_Config3_TL;
263     eBase.cpuNum = cp.CP0_EBase_CPUNum;
274     scsCtl.hss = cp.CP0_SrsCtl_HSS;
283     intCtl.ipti = cp.CP0_IntCtl_IPTI;
284     intCtl.ippci = cp.CP0_IntCtl_IPPCI;
293     watchHi.m = cp.CP0_WatchHi_M;
302     perfCntCtl.m = cp.CP0_PerfCtr_M;
303     perfCntCtl.w = cp.CP0_PerfCtr_W;
319     pageGrain.esp = cp.CP0_Config3_SP;