arch/mips/interrupts.cc

46 getCauseIP(ThreadContext *tc) {
47     CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
52 setCauseIP(ThreadContext *tc, uint8_t val) {
53     CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
55     tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
59 Interrupts::post(int int_num, ThreadContext* tc)
65     uint8_t intstatus = getCauseIP(tc);
67     setCauseIP(tc, intstatus);
77 Interrupts::clear(int int_num, ThreadContext* tc)
83     uint8_t intstatus = getCauseIP(tc);
85     setCauseIP(tc, intstatus);
95 Interrupts::clearAll(ThreadContext *tc)
99     setCauseIP(tc, intstatus);
110 Interrupts::checkInterrupts(ThreadContext *tc) const
112     if (!interruptsPending(tc))
116     StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
123         CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
133 Interrupts::getInterrupt(ThreadContext * tc)
135     assert(checkInterrupts(tc));
137     StatusReg M5_VAR_USED status = tc->readMiscRegNoEffect(MISCREG_STATUS);
138     CauseReg M5_VAR_USED cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
146 Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const
148     RegVal compare = tc->readMiscRegNoEffect(MISCREG_COMPARE);
149     RegVal count = tc->readMiscRegNoEffect(MISCREG_COUNT);
156 Interrupts::updateIntrInfo(ThreadContext *tc) const
162 Interrupts::interruptsPending(ThreadContext *tc) const
166     if (onCpuTimerInterrupt(tc)) {
167         DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");
169         IntCtlReg intCtl = tc->readMiscRegNoEffect(MISCREG_INTCTL);
170         uint8_t intStatus = getCauseIP(tc);
172         setCauseIP(tc, intStatus);
175     return (getCauseIP(tc) != 0);