arch/mips/faults.hh

88     virtual FaultVect offset(ThreadContext *tc) const = 0;
90     virtual FaultVect base(ThreadContext *tc) const
92         StatusReg status = tc->readMiscReg(MISCREG_STATUS);
94             return tc->readMiscReg(MISCREG_EBASE);
100     vect(ThreadContext *tc) const
102         return base(tc) + offset(tc);
105     void invoke(ThreadContext * tc, const StaticInstPtr &inst =
116     FaultVect offset(ThreadContext *tc) const { return vals.offset; }
137     void invoke(ThreadContext * tc, const StaticInstPtr &inst =
145     void invoke(ThreadContext * tc, const StaticInstPtr &inst =
152     void invoke(ThreadContext * tc, const StaticInstPtr &inst =
165     invoke(ThreadContext * tc, const StaticInstPtr &inst =
168         MipsFault<CoprocessorUnusableFault>::invoke(tc, inst);
170             CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
172             tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
181     offset(ThreadContext *tc) const
183         CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
200     invoke(ThreadContext * tc, const StaticInstPtr &inst =
203         MipsFault<T>::invoke(tc, inst);
205             tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
236     setTlbExceptionState(ThreadContext *tc, uint8_t excCode)
238         this->setExceptionState(tc, excCode);
240         tc->setMiscRegNoEffect(MISCREG_BADVADDR, this->vaddr);
241         EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
245         tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
247         ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
249         tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
253     invoke(ThreadContext * tc, const StaticInstPtr &inst =
258             Addr vect = this->vect(tc);
259             setTlbExceptionState(tc, this->code());
260             tc->pcState(vect);
262             AddressFault<T>::invoke(tc, inst);
281     offset(ThreadContext *tc) const
283         StatusReg status = tc->readMiscReg(MISCREG_STATUS);