arch/arm/utility.cc

58 initCPU(ThreadContext *tc, int cpuId)
65     reset->invoke(tc);
69 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
79     if (inAArch64(tc)) {
84                return tc->readIntReg(number);
102                 tmp = tc->readIntReg(number++);
103                 tmp |= tc->readIntReg(number) << 32;
106                return tc->readIntReg(number);
109             Addr sp = tc->readIntReg(StackPointerReg);
110             PortProxy &vp = tc->getVirtProxy();
131 skipFunction(ThreadContext *tc)
133     PCState newPC = tc->pcState();
134     if (inAArch64(tc)) {
135         newPC.set(tc->readIntReg(INTREG_X30));
137         newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
140     CheckerCPU *checker = tc->getCheckerCpuPtr();
142         tc->pcStateNoRecord(newPC);
144         tc->pcState(newPC);
196 inSecureState(ThreadContext *tc)
198     SCR scr = inAArch64(tc) ? tc->readMiscReg(MISCREG_SCR_EL3) :
199         tc->readMiscReg(MISCREG_SCR);
200     return ArmSystem::haveSecurity(tc) && inSecureState(
201         scr, tc->readMiscReg(MISCREG_CPSR));
205 isSecureBelowEL3(ThreadContext *tc)
207     SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
208     return ArmSystem::haveEL(tc, EL3) && scr.ns == 0;
212 inAArch64(ThreadContext *tc)
214     CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
219 longDescFormatInUse(ThreadContext *tc)
221     TTBCR ttbcr = tc->readMiscReg(MISCREG_TTBCR);
222     return ArmSystem::haveLPAE(tc) && ttbcr.eae;
226 readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
228     const ExceptionLevel current_el = currEL(tc);
230     const bool is_secure = isSecureBelowEL3(tc);
241         if (ArmSystem::haveEL(tc, EL2) && !is_secure)
242             return tc->readMiscReg(MISCREG_VMPIDR_EL2);
244             return getMPIDR(arm_sys, tc);
247         return getMPIDR(arm_sys, tc);
254 getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
267     assert((0 <= tc->cpuId()) && (tc->cpuId() < 256));
268     assert(tc->socketId() < 65536);
272               tc->contextId();
275               tc->cpuId() | tc->socketId() << 8;
279               tc->cpuId() | tc->socketId() << 8;
284 ELIs64(ThreadContext *tc, ExceptionLevel el)
286     return !ELIs32(tc, el);
290 ELIs32(ThreadContext *tc, ExceptionLevel el)
293     std::tie(known, aarch32) = ELUsingAArch32K(tc, el);
299 ELIsInHost(ThreadContext *tc, ExceptionLevel el)
301     if (!ArmSystem::haveVirtualization(tc)) {
304     HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
305     return (!isSecureBelowEL3(tc) && !ELIs32(tc, EL2) && hcr.e2h == 1 &&
310 ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
313     const bool have_el3 = ArmSystem::haveSecurity(tc);
314     const bool have_el2 = ArmSystem::haveVirtualization(tc);
321     if (ArmSystem::highestELIs64(tc) && ArmSystem::highestEL(tc) == el) {
325     } else if (!ArmSystem::highestELIs64(tc)) {
329         SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
332         HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
335                                && !isSecureBelowEL3(tc) && hcr.rw == 0));
340             CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
342             known = (currEL(tc) == EL0);
355 isBigEndian64(ThreadContext *tc)
357     switch (currEL(tc)) {
359         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).ee;
361         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).ee;
363         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).ee;
365         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).e0e;
373 badMode32(ThreadContext *tc, OperatingMode mode)
375     return unknownMode32(mode) || !ArmSystem::haveEL(tc, opModeToEL(mode));
379 badMode(ThreadContext *tc, OperatingMode mode)
381     return unknownMode(mode) || !ArmSystem::haveEL(tc, opModeToEL(mode));
385 purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
397         assert(ArmSystem::haveVirtualization(tc));
398         tcr = tc->readMiscReg(MISCREG_TCR_EL2);
403         assert(ArmSystem::haveSecurity(tc));
416 purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el)
423         tcr = tc->readMiscReg(MISCREG_TCR_EL1);
430         assert(ArmSystem::haveVirtualization(tc));
431         tcr = tc->readMiscReg(MISCREG_TCR_EL2);
436         assert(ArmSystem::haveSecurity(tc));
437         tcr = tc->readMiscReg(MISCREG_TCR_EL3);
462 mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss)
472     const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
473     const HCR hcr = tc->readMiscReg(MISCREG_HCR);
474     const SCR scr = tc->readMiscReg(MISCREG_SCR);
475     const HDCR hdcr = tc->readMiscReg(MISCREG_HDCR);
476     const HSTR hstr = tc->readMiscReg(MISCREG_HSTR);
477     const HCPTR hcptr = tc->readMiscReg(MISCREG_HCPTR);
583                 if (tc->getIsaPtr()->haveGICv3CpuIfc())
588                 if (tc->getIsaPtr()->haveGICv3CpuIfc())
819 SPAlignmentCheckEnabled(ThreadContext* tc)
821     switch (currEL(tc)) {
823         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).sa;
825         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).sa;
827         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa;
829         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa0;