arm/tracers/tarmac_parser.cc

646             value_lo = thread->readIntReg(it->index);
650                 value_lo = thread->readFloatReg(it->index * 4);
652                 value_lo = thread->readFloatReg(it->index);
656                 value_lo = thread->readFloatReg(it->index * 4) |
657                     (uint64_t) thread->readFloatReg(it->index * 4 + 1) <<
660                 value_lo = thread->readFloatReg(it->index * 2) |
661                     (uint64_t) thread->readFloatReg(it->index * 2 + 1) <<
667                 value_lo = thread->readFloatReg(it->index * 4) |
668                     (uint64_t) thread->readFloatReg(it->index * 4 + 1) <<
670                 value_hi = thread->readFloatReg(it->index * 4 + 2) |
671                     (uint64_t) thread->readFloatReg(it->index * 4 + 3) <<
674                 value_lo = thread->readFloatReg(it->index * 2) |
675                     (uint64_t) thread->readFloatReg(it->index * 2 + 1) <<
677                 value_hi = thread->readFloatReg(it->index * 2 + 2) |
678                     (uint64_t) thread->readFloatReg(it->index * 2 + 3) <<
685                 CPSR cpsr = thread->readMiscRegNoEffect(it->index);
686                 cpsr.nz = thread->readCCReg(CCREG_NZ);
687                 cpsr.c = thread->readCCReg(CCREG_C);
688                 cpsr.v = thread->readCCReg(CCREG_V);
689                 cpsr.ge = thread->readCCReg(CCREG_GE);
693                 cpsr.nz = thread->readCCReg(CCREG_NZ);
694                 cpsr.c = thread->readCCReg(CCREG_C);
695                 cpsr.v = thread->readCCReg(CCREG_V);
698                 value_lo = thread->readMiscRegNoEffect(it->index);
868                 parent, thread, staticInst, pc, mismatch,
1054     ArmISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
1056     req->setVirt(0, addr, size, flags, thread->pcState().instAddr(),
1060     Fault fault = dtb->translateAtomic(req, thread, BaseTLB::Read);
1074         thread->getVirtProxy().readBlob(addr, data, size);