arch/arm/tlb.cc

136 TLB::finalizePhysical(const RequestPtr &req,
139     const Addr paddr = req->getPaddr();
142         req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR);
143         req->setPaddr(GenericISA::iprAddressPseudoInst(
565 TLB::translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode,
569     Addr vaddr_tainted = req->getVaddr();
575     Request::Flags flags = req->getFlags();
581         assert(flags & MustBeOne || req->isPrefetch());
599     req->setPaddr(paddr);
601     return finalizePhysical(req, tc, mode);
605 TLB::checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode)
609     if (req->isCacheMaintenance()) {
613     Addr vaddr = req->getVaddr(); // 32-bit don't have to purify
614     Request::Flags flags = req->getFlags();
627     if (isStage2 && req->isPTWalk() && hcr.ptw &&
651         if (req->isPrefetch()) {
672                     req->getPC(),
766             req->getPC(),
783 TLB::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode,
793     if (req->isCacheClean() && aarch64EL != EL0 && !isStage2) {
797     Addr vaddr_tainted = req->getVaddr();
800     Request::Flags flags = req->getFlags();
803     bool is_write = !req->isCacheClean() && mode == Write;
804     bool is_atomic = req->isAtomic();
813     if (isStage2 && req->isPTWalk() && hcr.ptw &&
839         if (req->isPrefetch()) {
917                 if (checkPAN(tc, ap, req, mode)) {
957             if (hcr.e2h && checkPAN(tc, ap, req, mode)) {
997                 req->getPC(),
1016 TLB::checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req, Mode mode)
1027         (!req->isCacheMaintenance() ||
1028             (req->getFlags() & Request::CACHE_BLOCK_ZERO))) {
1036 TLB::translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode,
1045     Addr vaddr_tainted = req->getVaddr();
1051     Request::Flags flags = req->getFlags();
1059     req->setAsid(asid);
1068     if ((req->isInstFetch() && (!sctlr.i)) ||
1069         ((!req->isInstFetch()) && (!sctlr.c))){
1070         if (!req->isCacheMaintenance()) {
1071             req->setFlags(Request::UNCACHEABLE);
1073         req->setFlags(Request::STRICT_ORDER);
1076         assert(flags & MustBeOne || req->isPrefetch());
1092         req->setPaddr(vaddr);
1096             req->setFlags(Request::SECURE);
1101             if (!req->isCacheMaintenance()) {
1102                 req->setFlags(Request::UNCACHEABLE);
1104             req->setFlags(Request::STRICT_ORDER);
1133         return testTranslation(req, mode, TlbEntry::DomainType::NoAccess);
1142     Fault fault = getResultTe(&te, req, tc, mode, translation, timing,
1158         if (te->nonCacheable && !req->isCacheMaintenance())
1159             req->setFlags(Request::UNCACHEABLE);
1165             req->setFlags(Request::STRICT_ORDER);
1168         req->setPaddr(pa);
1171             req->setFlags(Request::SECURE);
1187             fault = testTranslation(req, mode, te->domain);
1193         return te ? finalizePhysical(req, tc, mode) : NoFault;
1200 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode,
1207         return stage2Tlb->translateAtomic(req, tc, mode, tranType);
1213         fault = translateFs(req, tc, mode, NULL, delay, false, tranType);
1215         fault = translateSe(req, tc, mode, NULL, delay, false);
1221 TLB::translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode,
1228         return stage2Tlb->translateFunctional(req, tc, mode, tranType);
1234         fault = translateFs(req, tc, mode, NULL, delay, false, tranType, true);
1236         fault = translateSe(req, tc, mode, NULL, delay, false);
1242 TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
1249         stage2Tlb->translateTiming(req, tc, translation, mode, tranType);
1255     translateComplete(req, tc, translation, mode, tranType, isStage2);
1259 TLB::translateComplete(const RequestPtr &req, ThreadContext *tc,
1266         fault = translateFs(req, tc, mode, translation, delay, true, tranType);
1268         fault = translateSe(req, tc, mode, translation, delay, true);
1277     if (translation && (callFromS2 || !stage2Req || req->hasPaddr() || fault != NoFault)) {
1279             translation->finish(fault, req, tc, mode);
1452 TLB::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode,
1464     Addr vaddr_tainted = req->getVaddr();
1474         if (req->isPrefetch()) {
1495         fault = tableWalker->walk(req, tc, asid, vmid, isHyp, mode,
1519 TLB::getResultTe(TlbEntry **te, const RequestPtr &req,
1531         fault = getTE(&s2Te, req, tc, mode, translation, timing, functional,
1536                 fault = checkPermissions64(s2Te, req, mode, tc);
1538                 fault = checkPermissions(s2Te, req, mode);
1546     Addr vaddr_tainted = req->getVaddr();
1549     fault = getTE(&s1Te, req, tc, mode, translation, timing, functional,
1555             fault = checkPermissions64(s1Te, req, mode, tc);
1557             fault = checkPermissions(s1Te, req, mode);
1560                 req, translation, mode, timing, functional, curTranType);
1577                         vaddr_tainted, req->hasPaddr() ? req->getPaddr() : ~0, fault);
1603 TLB::testTranslation(const RequestPtr &req, Mode mode,
1606     if (!test || !req->hasSize() || req->getSize() == 0 ||
1607         req->isCacheMaintenance()) {
1610         return test->translationCheck(req, isPriv, mode, domain);