arch/arm/tlb.cc

65 #include "debug/TLB.hh"
76 TLB::TLB(const ArmTLBParams *p)
98 TLB::~TLB()
104 TLB::init()
111 TLB::setMMU(Stage2MMU *m, MasterID master_id)
118 TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa)
136 TLB::finalizePhysical(const RequestPtr &req,
152 TLB::lookup(Addr va, uint16_t asn, uint8_t vmid, bool hyp, bool secure,
193 // insert a new TLB entry
195 TLB::insert(Addr addr, TlbEntry &entry)
197     DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x"
206         DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d vmn %d ppn %#x "
225 TLB::printTlb() const
229     DPRINTF(TLB, "Current TLB contents:\n");
233             DPRINTF(TLB, " *  %s\n", te->print());
239 TLB::flushAllSecurity(bool secure_lookup, ExceptionLevel target_el,
242     DPRINTF(TLB, "Flushing all TLB entries (%s lookup)\n",
254             DPRINTF(TLB, " -  %s\n", te->print());
263     // If there's a second stage TLB (and we're not it) then flush it as well
271 TLB::flushAllNs(ExceptionLevel target_el, bool ignore_el)
275     DPRINTF(TLB, "Flushing all NS TLB entries (%s lookup)\n",
286             DPRINTF(TLB, " -  %s\n", te->print());
295     // If there's a second stage TLB (and we're not it) then flush it as well
302 TLB::flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup,
305     DPRINTF(TLB, "Flushing TLB entries with mva: %#x, asid: %#x "
313 TLB::flushAsid(uint64_t asn, bool secure_lookup, ExceptionLevel target_el)
315     DPRINTF(TLB, "Flushing TLB entries with asid: %#x (%s lookup)\n", asn,
328             DPRINTF(TLB, " -  %s\n", te->print());
337 TLB::flushMva(Addr mva, bool secure_lookup, ExceptionLevel target_el)
339     DPRINTF(TLB, "Flushing TLB entries with mva: %#x (%s lookup)\n", mva,
346 TLB::_flushMva(Addr mva, uint64_t asn, bool secure_lookup,
359             DPRINTF(TLB, " -  %s\n", te->print());
369 TLB::flushIpaVmid(Addr ipa, bool secure_lookup, ExceptionLevel target_el)
376 TLB::drainResume()
384 TLB::takeOverFrom(BaseTLB *_otlb)
386     TLB *otlb = dynamic_cast<TLB*>(_otlb);
403         panic("Incompatible TLB type!");
408 TLB::serialize(CheckpointOut &cp) const
410     DPRINTF(Checkpoint, "Serializing Arm TLB\n");
425 TLB::unserialize(CheckpointIn &cp)
427     DPRINTF(Checkpoint, "Unserializing Arm TLB\n");
442 TLB::regStats()
507         .desc("Number of times complete TLB was flushed")
512         .desc("Number of times TLB was flushed by MVA")
517         .desc("Number of times TLB was flushed by MVA & ASID")
522         .desc("Number of times TLB was flushed by ASID")
527         .desc("Number of entries that have been flushed from TLB")
532         .desc("Number of TLB faults due to alignment restrictions")
537         .desc("Number of TLB faults due to prefetch")
542         .desc("Number of TLB faults due to domain restrictions")
547         .desc("Number of TLB faults due to permissions restrictions")
559 TLB::regProbePoints()
565 TLB::translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode,
605 TLB::checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode)
664             DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x"
707             DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n",
760         DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d "
771         DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d"
783 TLB::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode,
990             DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. "
1002             DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d "
1016 TLB::checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req, Mode mode)
1036 TLB::translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode,
1038         TLB::ArmTranslationType tranType, bool functional)
1064     DPRINTF(TLB, "translateFs addr %#x, mode %d, st2 %d, scr %#x sctlr %#x "
1200 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode,
1201     TLB::ArmTranslationType tranType)
1221 TLB::translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode,
1222     TLB::ArmTranslationType tranType)
1242 TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
1243     Translation *translation, Mode mode, TLB::ArmTranslationType tranType)
1259 TLB::translateComplete(const RequestPtr &req, ThreadContext *tc,
1260         Translation *translation, Mode mode, TLB::ArmTranslationType tranType,
1287 TLB::getTableWalkerPort()
1293 TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType)
1296     // NOTE: the tran type doesn't affect stage 2 TLB's as they only handle
1303     DPRINTF(TLBVerbose, "TLB variables changed!\n");
1423 TLB::tranTypeEL(CPSR cpsr, ArmTranslationType type)
1452 TLB::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode,
1454         bool is_secure, TLB::ArmTranslationType tranType)
1475             // if the request is a prefetch don't attempt to fill the TLB or go
1492         DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d:%d)\n",
1519 TLB::getResultTe(TlbEntry **te, const RequestPtr &req,
1527         // We are already in the stage 2 TLB. Grab the table entry for stage
1591 TLB::setTestInterface(SimObject *_ti)
1597         fatal_if(!ti, "%s is not a valid ARM TLB tester\n", _ti->name());
1603 TLB::testTranslation(const RequestPtr &req, Mode mode,
1615 TLB::testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode,
1627 ArmISA::TLB *
1630     return new ArmISA::TLB(this);