arch/arm/table_walker.cc

295         currState->ttbcr = currState->tc->readMiscReg(snsBankedIndex(
463             currState->vaddr_tainted, currState->ttbcr, mbits(currState->vaddr, 31,
464                                                       32 - currState->ttbcr.n));
468     if (currState->ttbcr.n == 0 || !mbits(currState->vaddr, 31,
469                                           32 - currState->ttbcr.n)) {
472         if (haveSecurity && currState->ttbcr.pd0) {
492         if (haveSecurity && currState->ttbcr.pd1) {
509         currState->ttbcr.n = 0;
512     Addr l1desc_addr = mbits(ttbr, 31, 14 - currState->ttbcr.n) |
513         (bits(currState->vaddr, 31 - currState->ttbcr.n, 20) << 2);
562             currState->vaddr_tainted, currState->ttbcr);
585         if (currState->ttbcr.t0sz)
586             ttbr0_max = (1ULL << (32 - currState->ttbcr.t0sz)) - 1;
587         else if (currState->ttbcr.t1sz)
589                 (1ULL << (32 - currState->ttbcr.t1sz)) - 1;
592         if (currState->ttbcr.t1sz)
593             ttbr1_min = (1ULL << 32) - (1ULL << (32 - currState->ttbcr.t1sz));
595             ttbr1_min = (1ULL << (32 - currState->ttbcr.t0sz));
606             if (currState->ttbcr.epd0) {
624             tsz = currState->ttbcr.t0sz;
630             if (currState->ttbcr.epd1) {
648             tsz = currState->ttbcr.t1sz;