arch/arm/table_walker.cc

131     tc(nullptr), aarch64(false), el(EL0), physAddrRange(0), req(nullptr),
232     currState->tc = _tc;
263                                             currState->tc, currState->el);
269             currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1);
270             currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR_EL2);
274             currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1);
275             currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL1);
279             currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2);
280             currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2);
284             currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL3);
285             currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL3);
291         currState->hcr = currState->tc->readMiscReg(MISCREG_HCR_EL2);
293         currState->sctlr = currState->tc->readMiscReg(snsBankedIndex(
294             MISCREG_SCTLR, currState->tc, !currState->isSecure));
295         currState->ttbcr = currState->tc->readMiscReg(snsBankedIndex(
296             MISCREG_TTBCR, currState->tc, !currState->isSecure));
297         currState->htcr  = currState->tc->readMiscReg(MISCREG_HTCR);
298         currState->hcr   = currState->tc->readMiscReg(MISCREG_HCR);
299         currState->vtcr  = currState->tc->readMiscReg(MISCREG_VTCR);
311                             longDescFormatInUse(currState->tc);
390         else if (longDescFormatInUse(currState->tc) ||
398                     curr_state_copy->tc, curr_state_copy->mode);
409     ThreadContext *tc = currState->tc;
423                 currState->req, currState->tc, currState->mode);
427             tlb->translateTiming(currState->req, currState->tc,
449     nextWalk(tc);
487         ttbr = currState->tc->readMiscReg(snsBankedIndex(
488             MISCREG_TTBR0, currState->tc, !currState->isSecure));
507         ttbr = currState->tc->readMiscReg(snsBankedIndex(
508             MISCREG_TTBR1, currState->tc, !currState->isSecure));
525             nextWalk(currState->tc);
528             currState->tc = NULL;
574         ttbr = currState->tc->readMiscReg(MISCREG_VTTBR);
579         ttbr = currState->tc->readMiscReg(MISCREG_HTTBR);
582         assert(longDescFormatInUse(currState->tc));
622             ttbr = currState->tc->readMiscReg(snsBankedIndex(
623                 MISCREG_TTBR0, currState->tc, !currState->isSecure));
646             ttbr = currState->tc->readMiscReg(snsBankedIndex(
647                 MISCREG_TTBR1, currState->tc, !currState->isSecure));
693             nextWalk(currState->tc);
696             currState->tc = NULL;
766             ttbr = currState->tc->readMiscReg(MISCREG_VTTBR_EL2);
788                 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1);
798                 ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1);
817             ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL2);
826             ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL2);
845                 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL3);
877             nextWalk(currState->tc);
880             currState->tc = NULL;
965             nextWalk(currState->tc);
968             currState->tc = NULL;
987             nextWalk(currState->tc);
990             currState->tc = NULL;
1024 TableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
1027     // Note: tc and sctlr local variables are hiding tc and sctrl class
1102         assert(tc);
1103         PRRR prrr = tc->readMiscReg(snsBankedIndex(MISCREG_PRRR,
1104                                     currState->tc, !currState->isSecure));
1105         NMRR nmrr = tc->readMiscReg(snsBankedIndex(MISCREG_NMRR,
1106                                     currState->tc, !currState->isSecure));
1231 TableWalker::memAttrsLPAE(ThreadContext *tc, TlbEntry &te,
1267         int reg_as_int = snsBankedIndex(reg, currState->tc,
1269         uint32_t mair = currState->tc->readMiscReg(reg_as_int);
1357 TableWalker::memAttrsAArch64(ThreadContext *tc, TlbEntry &te,
1399             mair = tc->readMiscReg(MISCREG_MAIR_EL1);
1402             mair = tc->readMiscReg(MISCREG_MAIR_EL2);
1405             mair = tc->readMiscReg(MISCREG_MAIR_EL3);
1463                                   byteOrder(currState->tc));
1475             currState->tc = NULL;
1529                     currState->tc = NULL;
1583                                     byteOrder(currState->tc));
1618             currState->tc = NULL;
1694                     currState->tc = NULL;
1741                                   byteOrder(currState->tc));
1752             currState->tc = NULL;
1811                                       currState->tc, currState->mode);
1815         nextWalk(currState->tc);
1818         currState->tc = NULL;
1827         tlb->translateTiming(currState->req, currState->tc,
1832         nextWalk(currState->tc);
1835         currState->tc = NULL;
1863                                       currState->tc, currState->mode);
1868         tlb->translateTiming(currState->req, currState->tc,
1876     nextWalk(currState->tc);
1879     currState->tc = NULL;
1932                                       currState->tc, currState->mode);
1935         nextWalk(currState->tc);
1938         currState->tc = NULL;
1945         tlb->translateTiming(currState->req, currState->tc,
1950         nextWalk(currState->tc);
1953         currState->tc = NULL;
1967 TableWalker::nextWalk(ThreadContext *tc)
1997             stage2Mmu->readDataTimed(currState->tc, descAddr, tran, numBytes,
2001             fault = stage2Mmu->readDataUntimed(currState->tc,
2022                            currState->tc->getCpuPtr()->clockPeriod(),flags);
2031                            currState->tc->getCpuPtr()->clockPeriod(), flags);
2094             memAttrsAArch64(currState->tc, te, lDescriptor);
2096             memAttrsLPAE(currState->tc, te, lDescriptor);
2099         memAttrs(currState->tc, te, currState->sctlr, descriptor.texcb(),
2118         currState->tc  = NULL;