Lines Matching refs:currState
63 currState(NULL), pending(false),
182 if (params()->sys->isTimingMode() && currState) {
183 delete currState;
184 currState = NULL;
201 if (!currState && !_functional) {
207 currState = new WalkerState();
208 currState->tableWalker = this;
214 savedCurrState = currState;
215 currState = new WalkerState();
216 currState->tableWalker = this;
224 if (currState->vaddr_tainted == _req->getVaddr()) {
231 currState->startTime = curTick();
232 currState->tc = _tc;
237 currState->el = EL1;
238 currState->aarch64 = ELIs64(_tc, EL2);
240 currState->el =
242 currState->aarch64 =
243 ELIs64(_tc, currState->el == EL0 ? EL1 : currState->el);
245 currState->transState = _trans;
246 currState->req = _req;
247 currState->fault = NoFault;
248 currState->asid = _asid;
249 currState->vmid = _vmid;
250 currState->isHyp = _isHyp;
251 currState->timing = _timing;
252 currState->functional = _functional;
253 currState->mode = _mode;
254 currState->tranType = tranType;
255 currState->isSecure = secure;
256 currState->physAddrRange = physAddrRange;
260 currState->vaddr_tainted = currState->req->getVaddr();
261 if (currState->aarch64)
262 currState->vaddr = purifyTaggedAddr(currState->vaddr_tainted,
263 currState->tc, currState->el);
265 currState->vaddr = currState->vaddr_tainted;
267 if (currState->aarch64) {
269 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1);
270 currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR_EL2);
271 } else switch (currState->el) {
274 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1);
275 currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL1);
279 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2);
280 currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2);
284 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL3);
285 currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL3);
291 currState->hcr = currState->tc->readMiscReg(MISCREG_HCR_EL2);
293 currState->sctlr = currState->tc->readMiscReg(snsBankedIndex(
294 MISCREG_SCTLR, currState->tc, !currState->isSecure));
295 currState->ttbcr = currState->tc->readMiscReg(snsBankedIndex(
296 MISCREG_TTBCR, currState->tc, !currState->isSecure));
297 currState->htcr = currState->tc->readMiscReg(MISCREG_HTCR);
298 currState->hcr = currState->tc->readMiscReg(MISCREG_HCR);
299 currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR);
301 sctlr = currState->sctlr;
303 currState->isFetch = (currState->mode == TLB::Execute);
304 currState->isWrite = (currState->mode == TLB::Write);
306 statRequestOrigin[REQUESTED][currState->isFetch]++;
308 currState->stage2Req = _stage2Req && !isStage2;
310 bool long_desc_format = currState->aarch64 || _isHyp || isStage2 ||
311 longDescFormatInUse(currState->tc);
315 currState->secureLookup = currState->isSecure;
316 currState->rwTable = true;
317 currState->userTable = true;
318 currState->xnTable = false;
319 currState->pxnTable = false;
326 if (!currState->timing) {
328 if (currState->aarch64)
337 if (currState->functional) {
338 delete currState;
339 currState = savedCurrState;
345 pendingQueue.push_back(currState);
346 currState = NULL;
351 if (currState->aarch64)
365 assert(!currState);
368 currState = pendingQueue.front();
372 TlbEntry* te = tlb->lookup(currState->vaddr, currState->asid,
373 currState->vmid, currState->isHyp, currState->isSecure, true, false,
374 currState->el);
381 if (!currState->transState->squashed() && !te) {
385 // Keep currState in case one of the processWalk... calls NULLs it
386 WalkerState *curr_state_copy = currState;
388 if (currState->aarch64)
390 else if (longDescFormatInUse(currState->tc) ||
391 currState->isHyp || isStage2)
409 ThreadContext *tc = currState->tc;
410 while ((num_squashed < numSquashable) && currState &&
411 (currState->transState->squashed() || te)) {
417 currState->vaddr_tainted);
419 if (currState->transState->squashed()) {
421 currState->transState->finish(
423 currState->req, currState->tc, currState->mode);
426 statWalkServiceTime.sample(curTick() - currState->startTime);
427 tlb->translateTiming(currState->req, currState->tc,
428 currState->transState, currState->mode);
433 delete currState;
437 currState = pendingQueue.front();
438 te = tlb->lookup(currState->vaddr, currState->asid,
439 currState->vmid, currState->isHyp, currState->isSecure, true,
440 false, currState->el);
443 currState = NULL;
450 currState = NULL;
459 assert(currState->sctlr.m || isStage2);
460 const bool is_atomic = currState->req->isAtomic();
463 currState->vaddr_tainted, currState->ttbcr, mbits(currState->vaddr, 31,
464 32 - currState->ttbcr.n));
466 statWalkWaitTime.sample(curTick() - currState->startTime);
468 if (currState->ttbcr.n == 0 || !mbits(currState->vaddr, 31,
469 32 - currState->ttbcr.n)) {
472 if (haveSecurity && currState->ttbcr.pd0) {
473 if (currState->isFetch)
475 currState->vaddr_tainted,
481 currState->vaddr_tainted,
483 is_atomic ? false : currState->isWrite,
487 ttbr = currState->tc->readMiscReg(snsBankedIndex(
488 MISCREG_TTBR0, currState->tc, !currState->isSecure));
492 if (haveSecurity && currState->ttbcr.pd1) {
493 if (currState->isFetch)
495 currState->vaddr_tainted,
501 currState->vaddr_tainted,
503 is_atomic ? false : currState->isWrite,
507 ttbr = currState->tc->readMiscReg(snsBankedIndex(
508 MISCREG_TTBR1, currState->tc, !currState->isSecure));
509 currState->ttbcr.n = 0;
512 Addr l1desc_addr = mbits(ttbr, 31, 14 - currState->ttbcr.n) |
513 (bits(currState->vaddr, 31 - currState->ttbcr.n, 20) << 2);
515 currState->isSecure ? "s" : "ns");
522 DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted);
523 if (currState->timing) {
525 nextWalk(currState->tc);
526 currState = NULL;
528 currState->tc = NULL;
529 currState->req = NULL;
535 if (currState->sctlr.c == 0) {
539 if (currState->isSecure) {
544 delayed = fetchDescriptor(l1desc_addr, (uint8_t*)&currState->l1Desc.data,
548 f = currState->fault;
562 currState->vaddr_tainted, currState->ttbcr);
564 statWalkWaitTime.sample(curTick() - currState->startTime);
567 if (currState->isSecure)
574 ttbr = currState->tc->readMiscReg(MISCREG_VTTBR);
575 tsz = sext<4>(currState->vtcr.t0sz);
576 start_lookup_level = currState->vtcr.sl0 ? L1 : L2;
577 } else if (currState->isHyp) {
579 ttbr = currState->tc->readMiscReg(MISCREG_HTTBR);
580 tsz = currState->htcr.t0sz;
582 assert(longDescFormatInUse(currState->tc));
585 if (currState->ttbcr.t0sz)
586 ttbr0_max = (1ULL << (32 - currState->ttbcr.t0sz)) - 1;
587 else if (currState->ttbcr.t1sz)
589 (1ULL << (32 - currState->ttbcr.t1sz)) - 1;
592 if (currState->ttbcr.t1sz)
593 ttbr1_min = (1ULL << 32) - (1ULL << (32 - currState->ttbcr.t1sz));
595 ttbr1_min = (1ULL << (32 - currState->ttbcr.t0sz));
597 const bool is_atomic = currState->req->isAtomic();
603 if (currState->vaddr <= ttbr0_max) {
606 if (currState->ttbcr.epd0) {
607 if (currState->isFetch)
609 currState->vaddr_tainted,
615 currState->vaddr_tainted,
617 is_atomic ? false : currState->isWrite,
622 ttbr = currState->tc->readMiscReg(snsBankedIndex(
623 MISCREG_TTBR0, currState->tc, !currState->isSecure));
624 tsz = currState->ttbcr.t0sz;
627 } else if (currState->vaddr >= ttbr1_min) {
630 if (currState->ttbcr.epd1) {
631 if (currState->isFetch)
633 currState->vaddr_tainted,
639 currState->vaddr_tainted,
641 is_atomic ? false : currState->isWrite,
646 ttbr = currState->tc->readMiscReg(snsBankedIndex(
647 MISCREG_TTBR1, currState->tc, !currState->isSecure));
648 tsz = currState->ttbcr.t1sz;
653 if (currState->isFetch)
655 currState->vaddr_tainted,
661 currState->vaddr_tainted,
663 is_atomic ? false : currState->isWrite,
674 (bits(currState->vaddr, n + 26, 30) << 3);
676 desc_addr, currState->isSecure ? "s" : "ns");
681 (bits(currState->vaddr, n + 17, 21) << 3);
683 desc_addr, currState->isSecure ? "s" : "ns");
690 DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted);
691 if (currState->timing) {
693 nextWalk(currState->tc);
694 currState = NULL;
696 currState->tc = NULL;
697 currState->req = NULL;
702 if (currState->sctlr.c == 0) {
706 currState->longDesc.lookupLevel = start_lookup_level;
707 currState->longDesc.aarch64 = false;
708 currState->longDesc.grainSize = Grain4KB;
710 bool delayed = fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data,
715 f = currState->fault;
741 assert(currState->aarch64);
744 currState->vaddr_tainted, currState->tcr);
751 statWalkWaitTime.sample(curTick() - currState->startTime);
761 switch (currState->el) {
766 ttbr = currState->tc->readMiscReg(MISCREG_VTTBR_EL2);
767 tsz = 64 - currState->vtcr.t0sz64;
768 tg = GrainMap_tg0[currState->vtcr.tg0];
773 uint8_t sl_tg = (currState->vtcr.sl0 << 2) | currState->vtcr.tg0;
783 ps = currState->vtcr.ps;
785 switch (bits(currState->vaddr, 63,48)) {
788 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1);
789 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
790 tg = GrainMap_tg0[currState->tcr.tg0];
791 currState->hpd = currState->tcr.hpd0;
792 if (bits(currState->vaddr, 63, tsz) != 0x0 ||
793 currState->tcr.epd0)
798 ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1);
799 tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz);
800 tg = GrainMap_tg1[currState->tcr.tg1];
801 currState->hpd = currState->tcr.hpd1;
802 if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) ||
803 currState->tcr.epd1)
810 ps = currState->tcr.ips;
814 switch(bits(currState->vaddr, 63,48)) {
817 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL2);
818 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
819 tg = GrainMap_tg0[currState->tcr.tg0];
820 currState->hpd = currState->hcr.e2h ?
821 currState->tcr.hpd0 : currState->tcr.hpd;
826 ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL2);
827 tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz);
828 tg = GrainMap_tg1[currState->tcr.tg1];
829 currState->hpd = currState->tcr.hpd1;
830 if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) ||
831 currState->tcr.epd1 || !currState->hcr.e2h)
839 ps = currState->tcr.ps;
842 switch(bits(currState->vaddr, 63,48)) {
845 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL3);
846 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
847 tg = GrainMap_tg0[currState->tcr.tg0];
848 currState->hpd = currState->tcr.hpd;
854 ps = currState->tcr.ps;
858 const bool is_atomic = currState->req->isAtomic();
862 if (currState->isFetch)
864 currState->vaddr_tainted,
869 currState->vaddr_tainted,
871 is_atomic ? false : currState->isWrite,
875 if (currState->timing) {
877 nextWalk(currState->tc);
878 currState = NULL;
880 currState->tc = NULL;
881 currState->req = NULL;
941 currState->physAddrRange = physAddrRange;
943 currState->physAddrRange = pa_range;
944 if (checkAddrSizeFaultAArch64(base_addr, currState->physAddrRange)) {
947 if (currState->isFetch)
949 currState->vaddr_tainted,
955 currState->vaddr_tainted,
957 is_atomic ? false : currState->isWrite,
963 if (currState->timing) {
965 nextWalk(currState->tc);
966 currState = NULL;
968 currState->tc = NULL;
969 currState->req = NULL;
977 (bits(currState->vaddr, tsz - 1,
984 DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted);
985 if (currState->timing) {
987 nextWalk(currState->tc);
988 currState = NULL;
990 currState->tc = NULL;
991 currState->req = NULL;
997 if (currState->sctlr.c == 0) {
1001 if (currState->isSecure) {
1005 currState->longDesc.lookupLevel = start_lookup_level;
1006 currState->longDesc.aarch64 = true;
1007 currState->longDesc.grainSize = tg;
1009 if (currState->timing) {
1010 fetchDescriptor(desc_addr, (uint8_t*) &currState->longDesc.data,
1014 fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data,
1017 f = currState->fault;
1104 currState->tc, !currState->isSecure));
1106 currState->tc, !currState->isSecure));
1267 int reg_as_int = snsBankedIndex(reg, currState->tc,
1268 !currState->isSecure);
1269 uint32_t mair = currState->tc->readMiscReg(reg_as_int);
1396 switch (currState->el) {
1458 if (currState->fault != NoFault) {
1462 currState->l1Desc.data = htog(currState->l1Desc.data,
1463 byteOrder(currState->tc));
1466 currState->vaddr_tainted, currState->l1Desc.data);
1469 const bool is_atomic = currState->req->isAtomic();
1471 switch (currState->l1Desc.type()) {
1474 if (!currState->timing) {
1475 currState->tc = NULL;
1476 currState->req = NULL;
1479 if (currState->isFetch)
1480 currState->fault =
1482 currState->vaddr_tainted,
1487 currState->fault =
1489 currState->vaddr_tainted,
1491 is_atomic ? false : currState->isWrite,
1496 if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) {
1502 currState->fault = std::make_shared<DataAbort>(
1503 currState->vaddr_tainted,
1504 currState->l1Desc.domain(),
1505 is_atomic ? false : currState->isWrite,
1510 if (currState->l1Desc.supersection()) {
1513 insertTableEntry(currState->l1Desc, false);
1518 l2desc_addr = currState->l1Desc.l2Addr() |
1519 (bits(currState->vaddr, 19, 12) << 2);
1521 l2desc_addr, currState->isSecure ? "s" : "ns");
1524 currState->fault = testWalk(l2desc_addr, sizeof(uint32_t),
1525 currState->l1Desc.domain(), L2);
1527 if (currState->fault) {
1528 if (!currState->timing) {
1529 currState->tc = NULL;
1530 currState->req = NULL;
1536 if (currState->isSecure)
1541 (uint8_t*)&currState->l2Desc.data,
1545 currState->delayed = true;
1558 if (currState->isFetch) {
1560 currState->vaddr_tainted,
1561 src + currState->longDesc.lookupLevel,
1566 currState->vaddr_tainted,
1568 currState->req->isAtomic() ? false : currState->isWrite,
1569 src + currState->longDesc.lookupLevel,
1578 if (currState->fault != NoFault) {
1582 currState->longDesc.data = htog(currState->longDesc.data,
1583 byteOrder(currState->tc));
1586 currState->longDesc.lookupLevel, currState->vaddr_tainted,
1587 currState->longDesc.data,
1588 currState->aarch64 ? "AArch64" : "long-desc.");
1590 if ((currState->longDesc.type() == LongDescriptor::Block) ||
1591 (currState->longDesc.type() == LongDescriptor::Page)) {
1594 currState->longDesc.lookupLevel,
1595 currState->longDesc.data,
1596 currState->longDesc.pxn(),
1597 currState->longDesc.xn(),
1598 currState->longDesc.ap(),
1599 currState->longDesc.af(),
1600 currState->longDesc.type());
1603 currState->longDesc.lookupLevel,
1604 currState->longDesc.data,
1605 currState->longDesc.type());
1610 switch (currState->longDesc.type()) {
1613 currState->longDesc.lookupLevel,
1614 ArmFault::TranslationLL + currState->longDesc.lookupLevel);
1616 currState->fault = generateLongDescFault(ArmFault::TranslationLL);
1617 if (!currState->timing) {
1618 currState->tc = NULL;
1619 currState->req = NULL;
1629 mbits(currState->longDesc.data, MaxPhysAddrRange - 1,
1630 currState->longDesc.offsetBits()),
1631 currState->physAddrRange)) {
1634 currState->longDesc.lookupLevel);
1638 } else if (currState->longDesc.af() == 0) {
1641 currState->longDesc.lookupLevel);
1646 currState->fault = generateLongDescFault(fault_source);
1648 insertTableEntry(currState->longDesc, true);
1655 currState->secureLookup = currState->secureLookup &&
1656 currState->longDesc.secureTable();
1657 currState->rwTable = currState->rwTable &&
1658 (currState->longDesc.rwTable() || currState->hpd);
1659 currState->userTable = currState->userTable &&
1660 (currState->longDesc.userTable() || currState->hpd);
1661 currState->xnTable = currState->xnTable ||
1662 (currState->longDesc.xnTable() && !currState->hpd);
1663 currState->pxnTable = currState->pxnTable ||
1664 (currState->longDesc.pxnTable() && !currState->hpd);
1667 Addr next_desc_addr = currState->longDesc.nextDescAddr(
1668 currState->vaddr);
1671 currState->longDesc.lookupLevel,
1672 currState->longDesc.lookupLevel + 1,
1674 currState->secureLookup ? "s" : "ns");
1677 if (currState->aarch64 && checkAddrSizeFaultAArch64(
1678 next_desc_addr, currState->physAddrRange)) {
1680 currState->longDesc.lookupLevel);
1682 currState->fault = generateLongDescFault(
1688 currState->fault = testWalk(
1690 toLookupLevel(currState->longDesc.lookupLevel +1));
1692 if (currState->fault) {
1693 if (!currState->timing) {
1694 currState->tc = NULL;
1695 currState->req = NULL;
1701 if (currState->secureLookup)
1704 LookupLevel L = currState->longDesc.lookupLevel =
1705 (LookupLevel) (currState->longDesc.lookupLevel + 1);
1709 assert(currState->aarch64);
1720 delayed = fetchDescriptor(next_desc_addr, (uint8_t*)&currState->longDesc.data,
1724 currState->delayed = true;
1736 if (currState->fault != NoFault) {
1740 currState->l2Desc.data = htog(currState->l2Desc.data,
1741 byteOrder(currState->tc));
1744 currState->vaddr_tainted, currState->l2Desc.data);
1747 const bool is_atomic = currState->req->isAtomic();
1749 if (currState->l2Desc.invalid()) {
1751 if (!currState->timing) {
1752 currState->tc = NULL;
1753 currState->req = NULL;
1755 if (currState->isFetch)
1756 currState->fault = std::make_shared<PrefetchAbort>(
1757 currState->vaddr_tainted,
1762 currState->fault = std::make_shared<DataAbort>(
1763 currState->vaddr_tainted, currState->l1Desc.domain(),
1764 is_atomic ? false : currState->isWrite,
1771 if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) {
1776 currState->sctlr.afe, currState->l2Desc.ap());
1778 currState->fault = std::make_shared<DataAbort>(
1779 currState->vaddr_tainted,
1781 is_atomic ? false : currState->isWrite,
1786 insertTableEntry(currState->l2Desc, false);
1792 currState = stateQueues[L1].front();
1793 currState->delayed = false;
1795 if (currState->stage2Tran) {
1796 delete currState->stage2Tran;
1797 currState->stage2Tran = NULL;
1801 DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data);
1802 DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data);
1804 DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr_tainted);
1809 if (currState->fault != NoFault) {
1810 currState->transState->finish(currState->fault, currState->req,
1811 currState->tc, currState->mode);
1815 nextWalk(currState->tc);
1817 currState->req = NULL;
1818 currState->tc = NULL;
1819 currState->delayed = false;
1820 delete currState;
1822 else if (!currState->delayed) {
1825 statWalkServiceTime.sample(curTick() - currState->startTime);
1827 tlb->translateTiming(currState->req, currState->tc,
1828 currState->transState, currState->mode);
1832 nextWalk(currState->tc);
1834 currState->req = NULL;
1835 currState->tc = NULL;
1836 currState->delayed = false;
1837 delete currState;
1840 stateQueues[L2].push_back(currState);
1842 currState = NULL;
1848 currState = stateQueues[L2].front();
1849 assert(currState->delayed);
1851 if (currState->stage2Tran) {
1852 delete currState->stage2Tran;
1853 currState->stage2Tran = NULL;
1857 currState->vaddr_tainted);
1861 if (currState->fault != NoFault) {
1862 currState->transState->finish(currState->fault, currState->req,
1863 currState->tc, currState->mode);
1866 statWalkServiceTime.sample(curTick() - currState->startTime);
1868 tlb->translateTiming(currState->req, currState->tc,
1869 currState->transState, currState->mode);
1876 nextWalk(currState->tc);
1878 currState->req = NULL;
1879 currState->tc = NULL;
1880 currState->delayed = false;
1882 delete currState;
1883 currState = NULL;
1913 currState = stateQueues[curr_lookup_level].front();
1914 assert(curr_lookup_level == currState->longDesc.lookupLevel);
1915 currState->delayed = false;
1918 if (currState->stage2Tran) {
1919 delete currState->stage2Tran;
1920 currState->stage2Tran = NULL;
1924 currState->vaddr_tainted);
1929 if (currState->fault != NoFault) {
1931 currState->transState->finish(currState->fault, currState->req,
1932 currState->tc, currState->mode);
1935 nextWalk(currState->tc);
1937 currState->req = NULL;
1938 currState->tc = NULL;
1939 currState->delayed = false;
1940 delete currState;
1941 } else if (!currState->delayed) {
1944 statWalkServiceTime.sample(curTick() - currState->startTime);
1945 tlb->translateTiming(currState->req, currState->tc,
1946 currState->transState, currState->mode);
1950 nextWalk(currState->tc);
1952 currState->req = NULL;
1953 currState->tc = NULL;
1954 currState->delayed = false;
1955 delete currState;
1960 stateQueues[currState->longDesc.lookupLevel].push_back(currState);
1962 currState = NULL;
1980 bool isTiming = currState->timing;
1983 descAddr, currState->stage2Req);
1988 if (currState->stage2Req) {
1995 currState->vaddr);
1996 currState->stage2Tran = tran;
1997 stage2Mmu->readDataTimed(currState->tc, descAddr, tran, numBytes,
2001 fault = stage2Mmu->readDataUntimed(currState->tc,
2002 currState->vaddr, descAddr, data, numBytes, flags,
2003 currState->functional);
2007 currState->fault = fault;
2013 stateQueues[queueIndex].push_back(currState);
2014 currState = NULL;
2022 currState->tc->getCpuPtr()->clockPeriod(),flags);
2026 stateQueues[queueIndex].push_back(currState);
2027 currState = NULL;
2029 } else if (!currState->functional) {
2031 currState->tc->getCpuPtr()->clockPeriod(), flags);
2056 te.isHyp = currState->isHyp;
2057 te.asid = currState->asid;
2058 te.vmid = currState->vmid;
2060 te.vpn = currState->vaddr >> te.N;
2065 te.ns = !descriptor.secure(haveSecurity, currState) || isStage2;
2066 te.nstid = !currState->isSecure;
2068 if (currState->aarch64)
2069 te.el = currState->el;
2074 statRequestOrigin[COMPLETED][currState->isFetch]++;
2078 te.global = descriptor.global(currState) || isStage2;
2083 te.xn |= currState->xnTable;
2084 te.pxn = currState->pxnTable || lDescriptor.pxn();
2090 te.ap = ((!currState->rwTable || descriptor.ap() >> 1) << 1) |
2091 (currState->userTable && (descriptor.ap() & 0x1));
2093 if (currState->aarch64)
2094 memAttrsAArch64(currState->tc, te, lDescriptor);
2096 memAttrsLPAE(currState->tc, te, lDescriptor);
2099 memAttrs(currState->tc, te, currState->sctlr, descriptor.texcb(),
2116 tlb->insert(currState->vaddr, te);
2117 if (!currState->timing) {
2118 currState->tc = NULL;
2119 currState->req = NULL;
2150 if ((currState != NULL) && (currState != pendingQueue.front())) {
2166 return tlb->testWalk(pa, size, currState->vaddr, currState->isSecure,
2167 currState->mode, domain, lookup_level);