arch/arm/table_walker.cc

77     sctlr = 0;
134     sctlr(0), scr(0), cpsr(0), tcr(0),
269             currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1);
274             currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1);
279             currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2);
284             currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL3);
293         currState->sctlr = currState->tc->readMiscReg(snsBankedIndex(
301     sctlr = currState->sctlr;
459     assert(currState->sctlr.m || isStage2);
535     if (currState->sctlr.c == 0) {
702     if (currState->sctlr.c == 0) {
997     if (currState->sctlr.c == 0) {
1024 TableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
1027     // Note: tc and sctlr local variables are hiding tc and sctrl class
1033     if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) {
1496         if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) {
1497             /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is
1771     if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) {
1772         /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled
1776                  currState->sctlr.afe, currState->l2Desc.ap());
2099         memAttrs(currState->tc, te, currState->sctlr, descriptor.texcb(),