arch/arm/pmu.hh

67  * Model of an ARM PMU version 3
69  * This class implements a subset of the ARM PMU v3 specification as
71  * features of the PMU, however the following features are known to be
76  *   <li>Access controls (the PMU currently ignores the execution level).
80  * The PMU itself does not implement any events, in merely provides an
89  * memory references synthesized from loads and stores), the PMU
91  * switches between CPU models that share the same PMU, PMU events for
92  * all of the CPU models can be registered with the PMU.
97 class PMU : public SimObject, public ArmISA::BaseISADevice {
99     PMU(const ArmPMUParams *p);
100     ~PMU();
119      * Set a register within the PMU.
126      * Read a register within the PMU.
133   protected: // PMU register types and constants
135         // PMU Enable
180      * Counter ID within the PMU.
194      * See the PMU documentation for a list of architected IDs.
205      * changes PMU-global state (e.g., resets all counters).
217      * Deliver a PMU interrupt to the GIC
222      * Clear a PMU interrupt.
257      * @param id Counter ID within the PMU.
272      * @param id Counter ID within the PMU.
306         void attachEvent(PMU::CounterState *user);
313         void detachEvent(PMU::CounterState *user);
343         std::set<PMU::CounterState*> userCounters;
411     /** State of a counter within the PMU. **/
413         CounterState(PMU &pmuReference, uint64_t counter_id)
493         PMU &pmu;
509      * @param id ID of counter within the PMU.
521      * @param id ID of counter within the PMU.
533      * @param id ID of counter within the PMU.
550      * @param id ID of counter within the PMU.
564      * Call updateCounter() for each counter in the PMU if the
602     /** State of all general-purpose counters supported by PMU */
625      * List of event types supported by this PMU.