arch/arm/pmu.cc

194 PMU::setMiscReg(int misc_reg, RegVal val)
197             miscRegName[unflattenMiscReg(misc_reg)], val);
202         setControlReg(val);
207         reg_pmcnten |= val;
213         reg_pmcnten &= ~val;
219         setOverflowStatus(reg_pmovsr & ~val);
225             swIncrementEvent->write(val);
231         cycleCounter.setValue(val);
236         reg_pmselr = val;
247         setCounterTypeRegister(misc_reg - MISCREG_PMEVTYPER0_EL0, val);
252         DPRINTF(PMUVerbose, "Setting PMCCFILTR: 0x%x\n", val);
253         setCounterTypeRegister(PMCCNTR, val);
261                 reg_pmselr, reg_pmselr.sel, val);
262         setCounterTypeRegister(reg_pmselr.sel, val);
266         setCounterValue(misc_reg - MISCREG_PMEVCNTR0_EL0, val);
271         setCounterValue(reg_pmselr.sel, val);
281         reg_pminten |= val;
286         reg_pminten &= ~val;
291         setOverflowStatus(reg_pmovsr | val);
305     RegVal val(readMiscRegInt(misc_reg));
307             miscRegName[unflattenMiscReg(misc_reg)], val);
308     return val;
402 PMU::setControlReg(PMCR_t val)
404     DPRINTF(PMUVerbose, "Set Control Reg 0x%08x.\n", val);
406     if (val.p) {
411     if (val.c) {
417     if (reg_pmcr.d != val.d)
420     reg_pmcr = val & reg_pmcr_wr_mask;
456 PMU::PMUEvent::increment(const uint64_t val)
459         counter->add(val);
474 PMU::RegularEvent::RegularProbe::notify(const uint64_t &val)
476     parentEvent->increment(val);
559 PMU::CounterState::setValue(uint64_t val)
561     value = val;
603 PMU::setCounterValue(CounterId id, uint64_t val)
612     ctr.setValue(val);
630 PMU::setCounterTypeRegister(CounterId id, PMEVTYPER_t val)
632     DPRINTF(PMUVerbose, "Set Event [%d] = 0x%08x\n", id, val);
642     ctr.filter = val;
647     if (id != PMCCNTR && old_event_id != val.evtCount) {
648         ctr.eventId = val.evtCount;
805 PMU::SWIncrementEvent::write(uint64_t val)
808         if (val & (0x1 << counter->getCounterId())) {