arch/arm/miscregs.cc

989 canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
997         canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
998                            miscRegInfo[reg][MISCREG_USR_NS_RD];
1006         canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1007                            miscRegInfo[reg][MISCREG_PRI_NS_RD];
1010         canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1011                            miscRegInfo[reg][MISCREG_MON_NS1_RD];
1014         canRead = miscRegInfo[reg][MISCREG_HYP_RD];
1020     assert(!miscRegInfo[reg][MISCREG_BANKED]);
1025 canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
1033         canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1034                             miscRegInfo[reg][MISCREG_USR_NS_WR];
1042         canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1043                             miscRegInfo[reg][MISCREG_PRI_NS_WR];
1046         canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1047                             miscRegInfo[reg][MISCREG_MON_NS1_WR];
1050         canWrite =  miscRegInfo[reg][MISCREG_HYP_WR];
1056     assert(!miscRegInfo[reg][MISCREG_BANKED]);
1061 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
1064     return snsBankedIndex(reg, tc, scr.ns);
1068 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
1070     int reg_as_int = static_cast<int>(reg);
1071     if (miscRegInfo[reg][MISCREG_BANKED]) {
1079 snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc)
1082     return tc->getIsaPtr()->snsBankedIndex64(reg, scr.ns);
1086  * If the reg is a child reg of a banked set, then the parent is the last
1098     int reg = -1;
1101             reg = i;
1103             unflattenResultMiscReg[i] = reg;
1112 unflattenMiscReg(int reg)
1114     return unflattenResultMiscReg[reg];
1118 canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1121     if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1125     if (reg == MISCREG_RVBAR_EL1) {
1130     if (reg == MISCREG_RVBAR_EL2) {
1140         return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
1141             miscRegInfo[reg][MISCREG_USR_NS_RD];
1143         return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1144             miscRegInfo[reg][MISCREG_PRI_NS_RD];
1146         return miscRegInfo[reg][MISCREG_HYP_RD];
1148         return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1149             miscRegInfo[reg][MISCREG_MON_NS1_RD];
1156 canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1159     if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1162     if (reg == MISCREG_DAIF) {
1167     if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
1174     if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
1184         return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1185             miscRegInfo[reg][MISCREG_USR_NS_WR];
1187         return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1188             miscRegInfo[reg][MISCREG_PRI_NS_WR];
1190         return miscRegInfo[reg][MISCREG_HYP_WR];
1192         return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1193             miscRegInfo[reg][MISCREG_MON_NS1_WR];