arch/arm/miscregs.cc

997         canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
998                            miscRegInfo[reg][MISCREG_USR_NS_RD];
1006         canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1007                            miscRegInfo[reg][MISCREG_PRI_NS_RD];
1010         canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1011                            miscRegInfo[reg][MISCREG_MON_NS1_RD];
1014         canRead = miscRegInfo[reg][MISCREG_HYP_RD];
1020     assert(!miscRegInfo[reg][MISCREG_BANKED]);
1033         canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1034                             miscRegInfo[reg][MISCREG_USR_NS_WR];
1042         canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1043                             miscRegInfo[reg][MISCREG_PRI_NS_WR];
1046         canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1047                             miscRegInfo[reg][MISCREG_MON_NS1_WR];
1050         canWrite =  miscRegInfo[reg][MISCREG_HYP_WR];
1056     assert(!miscRegInfo[reg][MISCREG_BANKED]);
1071     if (miscRegInfo[reg][MISCREG_BANKED]) {
1100         if (miscRegInfo[i][MISCREG_BANKED])
1102         if (miscRegInfo[i][MISCREG_BANKED_CHILD])
1140         return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
1141             miscRegInfo[reg][MISCREG_USR_NS_RD];
1143         return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1144             miscRegInfo[reg][MISCREG_PRI_NS_RD];
1146         return miscRegInfo[reg][MISCREG_HYP_RD];
1148         return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1149             miscRegInfo[reg][MISCREG_MON_NS1_RD];
1184         return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1185             miscRegInfo[reg][MISCREG_USR_NS_WR];
1187         return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1188             miscRegInfo[reg][MISCREG_PRI_NS_WR];
1190         return miscRegInfo[reg][MISCREG_HYP_WR];
1192         return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1193             miscRegInfo[reg][MISCREG_MON_NS1_WR];
2844 bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below