Lines Matching refs:vcpu
86 KvmKernelGicV2::setPPI(unsigned vcpu, unsigned ppi)
88 setIntState(KVM_ARM_IRQ_TYPE_PPI, vcpu, ppi, true);
92 KvmKernelGicV2::clearPPI(unsigned vcpu, unsigned ppi)
94 setIntState(KVM_ARM_IRQ_TYPE_PPI, vcpu, ppi, false);
98 KvmKernelGicV2::setIntState(unsigned type, unsigned vcpu, unsigned irq,
102 assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
106 (vcpu << KVM_ARM_IRQ_VCPU_SHIFT) |
113 KvmKernelGicV2::getGicReg(unsigned group, unsigned vcpu, unsigned offset)
117 assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
119 (vcpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) |
127 KvmKernelGicV2::setGicReg(unsigned group, unsigned vcpu, unsigned offset,
132 assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
134 (vcpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) |
143 auto vcpu = vm.contextIdToVCpuId(ctx);
144 return getGicReg(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, vcpu, daddr);
150 auto vcpu = vm.contextIdToVCpuId(ctx);
151 return getGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr);
157 auto vcpu = vm.contextIdToVCpuId(ctx);
158 setGicReg(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, vcpu, daddr, data);
164 auto vcpu = vm.contextIdToVCpuId(ctx);
165 setGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr, data);