arm/kvm/armv8_cpu.cc

65 #define INT_REG(name) CORE_REG(name, U64)
73     return INT_REG(regs.regs[0]) +
74         (INT_REG(regs.regs[1]) - INT_REG(regs.regs[0])) * num;
101     { INT_REG(regs.sp), INTREG_SP0, "SP(EL0)" },
102     { INT_REG(sp_el1), INTREG_SP1, "SP(EL1)" },
106     MiscRegInfo(INT_REG(elr_el1), MISCREG_ELR_EL1, "ELR(EL1)"),
107     MiscRegInfo(INT_REG(spsr[KVM_SPSR_EL1]), MISCREG_SPSR_EL1, "SPSR(EL1)"),
108     MiscRegInfo(INT_REG(spsr[KVM_SPSR_ABT]), MISCREG_SPSR_ABT, "SPSR(ABT)"),
109     MiscRegInfo(INT_REG(spsr[KVM_SPSR_UND]), MISCREG_SPSR_UND, "SPSR(UND)"),
110     MiscRegInfo(INT_REG(spsr[KVM_SPSR_IRQ]), MISCREG_SPSR_IRQ, "SPSR(IRQ)"),
111     MiscRegInfo(INT_REG(spsr[KVM_SPSR_FIQ]), MISCREG_SPSR_FIQ, "SPSR(FIQ)"),
112     MiscRegInfo(INT_REG(fp_regs.fpsr), MISCREG_FPSR, "FPSR"),
113     MiscRegInfo(INT_REG(fp_regs.fpcr), MISCREG_FPCR, "FPCR"),
152     inform("  PC: %s\n", getAndFormatOneReg(INT_REG(regs.pc)));
162     inform("  %s: %s\n", "PSTATE", getAndFormatOneReg(INT_REG(regs.pstate)));
231     setOneReg(INT_REG(regs.pstate), static_cast<uint64_t>(cpsr));
277     setOneReg(INT_REG(regs.pc), tc->instAddr());
287     const CPSR cpsr(getOneRegU64(INT_REG(regs.pstate)));
346     PCState pc(getOneRegU64(INT_REG(regs.pc)));