Lines Matching defs:tc
418 BaseISADevice &getGenericTimer(ThreadContext *tc);
419 BaseISADevice &getGICv3CPUInterface(ThreadContext *tc);
423 inline void assert32(ThreadContext *tc) {
424 CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
428 inline void assert64(ThreadContext *tc) {
429 CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
444 RegVal readMiscReg(int misc_reg, ThreadContext *tc);
446 void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc);
689 unsigned getCurSveVecLenInBits(ThreadContext *tc) const;
731 void startup(ThreadContext *tc);