Lines Matching defs:reg
370 const MiscRegLUTEntryInitializer InitReg(uint32_t reg) {
371 return MiscRegLUTEntryInitializer(lookUpMiscReg[reg],
372 miscRegInfo[reg]);
473 flattenIntIndex(int reg) const
475 assert(reg >= 0);
476 if (reg < NUM_ARCH_INTREGS) {
477 return intRegMap[reg];
478 } else if (reg < NUM_INTREGS) {
479 return reg;
480 } else if (reg == INTREG_SPX) {
500 return flattenIntRegModeIndex(reg);
505 flattenFloatIndex(int reg) const
507 assert(reg >= 0);
508 return reg;
512 flattenVecIndex(int reg) const
514 assert(reg >= 0);
515 return reg;
519 flattenVecElemIndex(int reg) const
521 assert(reg >= 0);
522 return reg;
526 flattenVecPredIndex(int reg) const
528 assert(reg >= 0);
529 return reg;
533 flattenCCIndex(int reg) const
535 assert(reg >= 0);
536 return reg;
540 flattenMiscIndex(int reg) const
542 assert(reg >= 0);
543 int flat_idx = reg;
545 if (reg == MISCREG_SPSR) {
595 } else if (miscRegInfo[reg][MISCREG_MUTEX]) {
597 switch (reg) {
603 // If the muxed reg has been flattened, work out the
604 // offset and apply it to the unmuxed reg
605 int idxOffset = reg - MISCREG_PRRR_MAIR0;
619 // If the muxed reg has been flattened, work out the
620 // offset and apply it to the unmuxed reg
621 int idxOffset = reg - MISCREG_NMRR_MAIR1;
644 if (miscRegInfo[reg][MISCREG_BANKED]) {
650 flat_idx = snsBankedIndex64((MiscRegIndex)reg,
659 snsBankedIndex64(MiscRegIndex reg, bool ns) const
661 int reg_as_int = static_cast<int>(reg);
662 if (miscRegInfo[reg][MISCREG_BANKED64]) {