arm/insts/static_inst.cc

632     const auto tc = xc->tcBase();
633     const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
634     const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
635     if ((ArmSystem::haveEL(tc, EL2) && !inSecureState(tc) &&
636          !ELIs32(tc, EL2) && (hcr.tge == 1 || mdcr.tde == 1)) ||
637          !ELIs32(tc, EL1)) {
668 ArmStaticInst::checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const
670     if (ArmSystem::haveVirtualization(tc) && !inSecureState(tc)) {
671         HCPTR cptrEnCheck = tc->readMiscReg(MISCREG_CPTR_EL2);
676     if (ArmSystem::haveSecurity(tc)) {
677         HCPTR cptrEnCheck = tc->readMiscReg(MISCREG_CPTR_EL3);
686 ArmStaticInst::checkFPAdvSIMDEnabled64(ThreadContext *tc,
689     const ExceptionLevel el = currEL(tc);
694     return checkFPAdvSIMDTrap64(tc, cpsr);
698 ArmStaticInst::checkAdvSIMDOrFPEnabled32(ThreadContext *tc,
703     const bool have_virtualization = ArmSystem::haveVirtualization(tc);
704     const bool have_security = ArmSystem::haveSecurity(tc);
705     const bool is_secure = inSecureState(tc);
706     const ExceptionLevel cur_el = currEL(tc);
708     if (cur_el == EL0 && ELIs64(tc, EL1))
709         return checkFPAdvSIMDEnabled64(tc, cpsr, cpacr);
714     if (have_security && !ELIs64(tc, EL3) && !is_secure) {
735     if (have_virtualization && !is_secure && ELIs64(tc, EL2))
736         return checkFPAdvSIMDTrap64(tc, cpsr);
739         HCPTR hcptr = tc->readMiscReg(MISCREG_HCPTR);
743         if (have_security && !ELIs64(tc, EL3) && !is_secure) {
765     if (have_security && ELIs64(tc, EL3)) {
766         HCPTR cptrEnCheck = tc->readMiscReg(MISCREG_CPTR_EL3);
775 ArmStaticInst::isWFxTrapping(ThreadContext *tc,
780     SCTLR sctlr = ((SCTLR)tc->readMiscReg(MISCREG_SCTLR_EL1));
781     HCR hcr = ((HCR)tc->readMiscReg(MISCREG_HCR_EL2));
782     SCR scr = ((SCR)tc->readMiscReg(MISCREG_SCR_EL3));
802 ArmStaticInst::checkForWFxTrap32(ThreadContext *tc,
807     assert(ArmSystem::haveEL(tc, targetEL));
812     if (ELIs64(tc, targetEL)) {
813         return checkForWFxTrap64(tc, targetEL, isWfe);
817     bool trap = isWFxTrapping(tc, targetEL, isWfe);
842 ArmStaticInst::checkForWFxTrap64(ThreadContext *tc,
847     assert(ArmSystem::haveEL(tc, targetEL));
850     bool trap = isWFxTrapping(tc, targetEL, isWfe);
874 ArmStaticInst::trapWFx(ThreadContext *tc,
879     ExceptionLevel curr_el = currEL(tc);
882         fault = checkForWFxTrap32(tc, EL1, isWfe);
886         ArmSystem::haveEL(tc, EL2) && !inSecureState(scr, cpsr) &&
889         fault = checkForWFxTrap32(tc, EL2, isWfe);
893         ArmSystem::haveEL(tc, EL3) && curr_el != EL3) {
894         fault = checkForWFxTrap32(tc, EL3, isWfe);
901 ArmStaticInst::checkSETENDEnabled(ThreadContext *tc, CPSR cpsr) const
904     ExceptionLevel pstate_el = currEL(tc);
907        setend_disabled = ((SCTLR)tc->readMiscRegNoEffect(MISCREG_HSCTLR)).sed;
922             MISCREG_SCTLR, tc, !inSecureState(tc));
925         setend_disabled = ((SCTLR)tc->readMiscRegNoEffect(banked_sctlr)).sed;
928     return setend_disabled ? undefinedFault32(tc, pstate_el) :
933 ArmStaticInst::undefinedFault32(ThreadContext *tc,
938     if (generalExceptionsToAArch64(tc, pstateEL)) {
939         return undefinedFault64(tc, pstateEL);
952 ArmStaticInst::undefinedFault64(ThreadContext *tc,
989 ArmStaticInst::checkSveTrap(ThreadContext *tc, CPSR cpsr) const
993     if (ArmSystem::haveVirtualization(tc) && el <= EL2) {
994         CPTR cptrEnCheck = tc->readMiscReg(MISCREG_CPTR_EL2);
999     if (ArmSystem::haveSecurity(tc)) {
1000         CPTR cptrEnCheck = tc->readMiscReg(MISCREG_CPTR_EL3);
1009 ArmStaticInst::checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
1016     return checkSveTrap(tc, cpsr);
1021 getRestoredITBits(ThreadContext *tc, CPSR spsr)
1037         ((SCTLR)tc->readMiscReg(MISCREG_HSCTLR)).itd :
1038         ((SCTLR)tc->readMiscReg(MISCREG_SCTLR)).itd;
1050 illegalExceptionReturn(ThreadContext *tc, CPSR cpsr, CPSR spsr)
1059     HCR hcr = ((HCR)tc->readMiscReg(MISCREG_HCR_EL2));
1060     SCR scr = ((SCR)tc->readMiscReg(MISCREG_SCR_EL3));
1065     if (!ArmSystem::haveEL(tc, target_el))
1068     if (target_el == EL1 && ArmSystem::haveEL(tc, EL2) && scr.ns && hcr.tge)
1071     if (target_el == EL2 && ArmSystem::haveEL(tc, EL3) && !scr.ns)
1076     std::tie(known, target_el_is_aarch32) = ELUsingAArch32K(tc, target_el);
1077     assert(known || (target_el == EL0 && ELIs64(tc, EL1)));
1084         if (!ArmSystem::highestELIs64(tc))
1099 ArmStaticInst::getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const
1107     if (illegalExceptionReturn(tc, cpsr, spsr)) {
1137         const ITSTATE it = getRestoredITBits(tc, spsr);
1154 ArmStaticInst::generalExceptionsToAArch64(ThreadContext *tc,
1160     HCR hcr = ((HCR)tc->readMiscReg(MISCREG_HCR_EL2));
1161     return (pstateEL == EL0 && !ELIs32(tc, EL1)) ||
1162            (ArmSystem::haveEL(tc, EL2) && !inSecureState(tc) &&
1163                !ELIs32(tc, EL2) && hcr.tge);
1167 ArmStaticInst::getCurSveVecLenInBits(ThreadContext *tc)
1169     return tc->getIsaPtr()->getCurSveVecLenInBits(tc);