Lines Matching refs:sc_core
97 #define TLM_FULL_ARG_LIST typename TRAITS::tlm_payload_type& txn, typename TRAITS::tlm_phase_type& ph, sc_core::sc_time& t
105 #define TLM_FULL_ARG_LIST typename TRAITS::tlm_payload_type& txn, sc_core::sc_time& t
165 sc_core::sc_time& t){
177 void b_transport(transaction_type& trans,sc_core::sc_time& t){
212 void register_port(sc_core::sc_port_base& b, const char* name){
227 sc_core::sc_port_base* get_other_side(){return m_caller_port;}
240 sc_core::sc_port_base* m_caller_port;
268 sc_core::sc_time& t){
312 ,sc_core::sc_port_policy POL = sc_core::SC_ONE_OR_MORE_BOUND
349 multi_init_base():base_type(sc_core::sc_gen_unique_name("multi_init_base")){}
362 ,sc_core::sc_port_policy POL = sc_core::SC_ONE_OR_MORE_BOUND
401 multi_target_base():base_type(sc_core::sc_gen_unique_name("multi_target_base")){}