Lines Matching refs:interface_ip
322 writeBuffer(NULL), MC_arb(NULL), interface_ip(*interface_ip_),
338 interface_ip.cache_sz = data * mcp.req_window_size_per_channel;
339 interface_ip.line_sz = data;
340 interface_ip.assoc = mcp.reorder_buffer_assoc;
341 interface_ip.nbanks = mcp.reorder_buffer_nbanks;
342 interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE;
343 interface_ip.specific_tag = tag > 0;
344 interface_ip.tag_w = tag;
345 interface_ip.access_mode = Normal;
346 interface_ip.obj_func_dyn_energy = 0;
347 interface_ip.obj_func_dyn_power = 0;
348 interface_ip.obj_func_leak_power = 0;
349 interface_ip.obj_func_cycle_t = 1;
350 interface_ip.num_rw_ports = 0;
351 interface_ip.num_rd_ports = mcp.num_channels;
352 interface_ip.num_wr_ports = interface_ip.num_rd_ports;
353 interface_ip.num_se_rd_ports = 0;
354 interface_ip.num_search_ports = mcp.num_channels;
355 interface_ip.is_cache = true;
356 interface_ip.pure_cam = false;
357 interface_ip.pure_ram = false;
358 interface_ip.throughput = 1.0 / mcp.clockRate;
359 interface_ip.latency = 1.0 / mcp.clockRate;
360 frontendBuffer = new CacheArray(xml_data, &interface_ip, "Reorder Buffer",
392 interface_ip.cache_sz = data * mcp.IO_buffer_size_per_channel;
393 interface_ip.line_sz = data;
394 interface_ip.assoc = mcp.read_buffer_assoc;
395 interface_ip.nbanks = mcp.read_buffer_nbanks;
396 interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE;
397 interface_ip.specific_tag = mcp.read_buffer_tag_width > 0;
398 interface_ip.tag_w = mcp.read_buffer_tag_width;
399 interface_ip.access_mode = Sequential;
400 interface_ip.obj_func_dyn_energy = 0;
401 interface_ip.obj_func_dyn_power = 0;
402 interface_ip.obj_func_leak_power = 0;
403 interface_ip.obj_func_cycle_t = 1;
404 interface_ip.num_rw_ports = 0;
405 interface_ip.num_rd_ports = mcp.num_channels;
406 interface_ip.num_wr_ports = interface_ip.num_rd_ports;
407 interface_ip.num_se_rd_ports = 0;
408 interface_ip.num_search_ports = 0;
409 interface_ip.is_cache = false;
410 interface_ip.pure_cam = false;
411 interface_ip.pure_ram = true;
412 interface_ip.throughput = 1.0 / mcp.clockRate;
413 interface_ip.latency = 1.0 / mcp.clockRate;
414 readBuffer = new CacheArray(xml_data, &interface_ip, "Read Buffer",
433 interface_ip.cache_sz = data * mcp.IO_buffer_size_per_channel;
434 interface_ip.line_sz = data;
435 interface_ip.assoc = mcp.write_buffer_assoc;
436 interface_ip.nbanks = mcp.write_buffer_nbanks;
437 interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE;
438 interface_ip.specific_tag = mcp.write_buffer_tag_width > 0;
439 interface_ip.tag_w = mcp.write_buffer_tag_width;
440 interface_ip.access_mode = Normal;
441 interface_ip.obj_func_dyn_energy = 0;
442 interface_ip.obj_func_dyn_power = 0;
443 interface_ip.obj_func_leak_power = 0;
444 interface_ip.obj_func_cycle_t = 1;
445 interface_ip.num_rw_ports = 0;
446 interface_ip.num_rd_ports = mcp.num_channels;
447 interface_ip.num_wr_ports = interface_ip.num_rd_ports;
448 interface_ip.num_se_rd_ports = 0;
449 interface_ip.num_search_ports = 0;
450 interface_ip.is_cache = false;
451 interface_ip.pure_cam = false;
452 interface_ip.pure_ram = true;
453 interface_ip.throughput = 1.0 / mcp.clockRate;
454 interface_ip.latency = 1.0 / mcp.clockRate;
455 writeBuffer = new CacheArray(xml_data, &interface_ip, "Write Buffer",
474 mcp.req_window_size_per_channel, 1, &interface_ip,
483 : McPATComponent(_xml_data), interface_ip(*interface_ip_) {
487 children.push_back(new MCFrontEnd(xml_data, &interface_ip, mcp, mcs));
488 children.push_back(new MCBackend(xml_data, &interface_ip, mcp, mcs));
491 children.push_back(new MCPHY(xml_data, &interface_ip, mcp, mcs));
541 ASSIGN_ENUM_IF("wire_type", interface_ip.wt, Wire_type);
557 interface_ip.data_arr_ram_cell_tech_type = tech_type;
558 interface_ip.data_arr_peri_global_tech_type = tech_type;
559 interface_ip.tag_arr_ram_cell_tech_type = tech_type;
560 interface_ip.tag_arr_peri_global_tech_type = tech_type;
561 interface_ip.wire_is_mat_type = mat_type;
562 interface_ip.wire_os_mat_type = mat_type;